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Computing system for unified memory access

A computing system and memory access technology, applied in the field of computing systems, can solve the problems of reducing optimization and prohibiting optimization opportunities, etc., and achieve the effect of effective and efficient control

Active Publication Date: 2020-06-05
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Furthermore, the potential benefits of heterogeneity cannot be fully exploited at runtime because they require explicit addressing at programming and application development time, reducing opportunities for further optimization
[0010] Disadvantages of prior art solutions are: forcing application developers to adopt a specific programming model, requiring software modifications; targeting specific heterogeneous environments, precluding running in several potentially available accelerator environments that can be co-hosted possibility; prohibits optimization opportunities that can be determined at runtime of the application

Method used

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  • Computing system for unified memory access
  • Computing system for unified memory access
  • Computing system for unified memory access

Examples

Experimental program
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Embodiment Construction

[0069] figure 1 A computing system 100 is shown in accordance with an embodiment of the invention. The computing system 100 allows unified memory access and includes a first processing unit 101 , a second processing unit 102 , and a shared memory 103 including a first memory segment 104 and a second memory segment 105 .

[0070] Thus, both processing units 101 and 102 may be, for example, one of the following: a CPU, a CPU core, a GPU, a GPU core, a near data processor, a CPU connected to a coherent interconnect, a CPU interconnected via a peripheral bus An accelerator, a remote processing unit (eg, a near-data processor, CPU, or GPU), or a kernel (eg, the kernel of an OS) connected via an RDMA-capable interface. The computing system 100 may include any number of processing units as long as it includes at least the first processing unit 101 and the second processing unit 102 as defined above, for example.

[0071] Optionally, the first processing unit 101 and the second pro...

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PUM

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Abstract

The invention provides a computing system (100) for unified memory access, comprising a first processing unit (101) and a second processing unit (102), a shared memory (103) including a first memory segment (104) and a second memory segment (105), an operating system (106), operated at least partly by the first processing unit (101), and an application (107), operated at least partly by the operating system (106). The first processing unit (101) and the second processing unit (102) are connected to the shared memory (103). The operating system (106) is configured to control at least one of thefirst processing unit (101) and the second processing unit (102), and the shared memory (103), based on requirements information comprised in the operating system (106) and / or the application (107),to allocate the first memory segment (104) to at least a part of the application (107), wherein the requirements information comprises executable binary code that comprises information regarding a type and / or a state of a memory segment required by at least a part of the application (107).

Description

technical field [0001] The invention relates to a computing system for unified memory access and a corresponding method. In particular, the systems and methods of the present invention affect the manner in which an operating system (OS) allocates shared memory based on demand information in a multiprocessor system. Preferably, the requirement information includes executable binary code, and the executable binary code includes information about the type and / or status of at least a part of the memory segments required by the application. Background technique [0002] Emerging computer architectures are characterized by increasing heterogeneity in memory and processor subsystems, primarily due to novel memory technologies, low-latency load / store access interconnects, and near data processing (NDP) Resurgent, near-data processing is introduced along the memory hierarchy into processing units. [0003] Addressable memory includes on-chip memory, off-chip memory (for example, co...

Claims

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Application Information

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IPC IPC(8): G06F8/41G06F9/445G06F9/50
CPCG06F12/0877G06F13/1663G06F12/023G06F8/451G06F8/454G06F9/44521G06F9/5083G06F9/5088
Inventor 安东尼奥·巴巴拉斯安东尼·利奥普洛斯
Owner HUAWEI TECH CO LTD