Projectile penetration high-impact overload testing device and method

Abstract

The invention discloses a projectile penetration high-impact overload testing device. The device comprises a software system, a hardware system and a protection structure, wherein the software systeminvolves upper computer control and data read-back analysis software and lower computer embedded type software, the hardware system is used for executing the protection structure of the lower computerembedded type software, and the protection structure is arranged in an inner cavity of a projectile. The invention also discloses a projectile penetration high-impact overload testing method. The method is applied to the projectile penetration high-impact overload testing device. The invention relates to the projectile penetration high-impact overload testing device and method. The device and themethod are suitable for micro power battery power supply and projectile penetration ultrahigh impact overload signal testing, are suitable for testing occasions where impact overload testing of various types of projectile penetration experiments has strict control requirements on the size and standby duration of the testing device, and can be widely applied to the technical fields of projectile penetration high-impact overload testing, drop impact testing, horizontal impact experiment testing and conventional storage testing.

Description

technical field [0001] The invention relates to the technical field of dynamic / transient shooting range testing, in particular to a shell penetration high impact overload testing device and method. Background technique [0002] The shell impact overload test is mainly used to study the dynamic and transient response transfer law of the internal structure of the shell during the process of penetrating the target, and provides important technical support for the study and assessment of the dynamic behavior of the shell. Usually, artillery shells are fired at high speeds to act on steel or concrete targets for testing. This special loading method determines that the integrated signal test solution of wired cables cannot be used. Consider using a bomb-loaded embedded test system. [0003] At present, for the design of the missile-borne embedded test system, the logic control device based on CPLD and FPGA is mainly used as the core controller, and the peripheral A / D converter, am...

AI Technical Summary

Problems solved by technology

This test scheme is more suitable for large-scale test multi-channel signal test and test occasions where the size and power consumption of the test device are not limited, but it is insufficient for the test of high impact overload. The main performance is as follows: CPLD, FPGA and other devices that realize complex functions The size is usually large. Currently, the smallest CPLD device is 7mm×7mm, but the number of logic units does not exceed 600. It is obviously insufficient for sequential logic resources such as A / D acquisition, storage, data transmission readback, and signal mode detection at the same time. , which brings great difficulties to the complex function design of the test device; second, CPLD and FPGA devices with sufficient logic resources are usually large in size and high in power, and there are many types of power supplies to be provided. After adding various peripheral chips, the designed circuit The board area is larger, which brings higher challenges to the design of subsequent high-impact overload protection devices; third, CPLD and FPGA need JTAG download lines to realize field programmable program downloads, which requires JTAG interfaces to be reserved during device interface design. The JTAG transmission cable is added, and the USB transmission cable and analog signal cable are added at the same time. The signal cables reach more than ten or more, which reduces the reliability of the device and is not conducive to the miniaturization design of the test device. If the JTAG program download is reduced After the device design is completed, the program is programmed into the CPLD or FPGA configuration chip at one time. It is undoubtedly necessary to add additional memory to the hardware to store special test parameters, and the programming is complicated, which may lead to insufficient logic device resources. Happening

For the special test environment with high impact and overload, the key requirements are that the test device must meet the three conditions of small size, few signal cables, and extremely low power consumption. The implementation technology of traditional CPLD and FPGA embedded controllers has shortcomings and is not the best. Excellent solution

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