System and method for test planning based on hypercube topology in network-on-chip

Abstract

The invention discloses a test planning system and method based on a hypercube topology in an on-chip network, including an IP core extraction module, an IP core encoding module, an input port allocation module, a path algorithm module, and an output port allocation module And the data analysis module, the IP core extraction module extracts the test IP core in the circuit to be tested and the parameters required for testing, and encodes and maps the IP core with a hypercube structure through the IP core encoding module, and the test vector is allocated by the input port The module is assigned to the designated port, and then the path algorithm module uses the E-cube algorithm with partial self-adaptive ability to plan the path, tests the IP core, and the test results are planned and sent to the output by the E-cube algorithm with partial self-adaptive ability Port assignment mod. By reducing the number of routers passing through the test process, the distance between IP cores and the diversity of routing node selection in the data transmission process, the test time of IP cores is reduced and the test efficiency is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a test planning system and method based on a hypercube topology in an on-chip network. Background technique [0002] The specific test process of the on-chip network is as follows: first, the test vector enters the topology structure from the input port, and is transmitted to the IP core to be tested by a certain routing strategy and waits for the test to be completed, and then the test response of the IP core is passed through the topology structure again with a certain routing algorithm. transmitted to the output port for analysis. [0003] The topology structure reflects the connection and layout of communication nodes, which will affect the communication delay and network throughput of the on-chip network; the routing algorithm determines the transmission path of the message in the network, and a good routing algorithm can improve the performance of the interconnecte...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a test planning system and method based on a hypercube topology in an on-chip network, aiming to solve the problem of low test efficiency caused by the long time spent in the process of testing the on-chip network using traditional structural algorithms

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