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Preparation method of deep trench isolation structure and semiconductor device

A deep trench isolation and trench technology, which is applied in the field of preparation of deep trench isolation structures, can solve the problems of long thermal advance time at high temperature and high manufacturing cost

Pending Publication Date: 2020-06-30
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The present application provides a preparation method of a deep trench isolation structure and a deep trench isolation structure, which can solve the manufacturing cost of the deep trench isolation structure provided in the related art due to the long time of high-temperature thermal advance in the preparation process higher question

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  • Preparation method of deep trench isolation structure and semiconductor device
  • Preparation method of deep trench isolation structure and semiconductor device
  • Preparation method of deep trench isolation structure and semiconductor device

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Embodiment Construction

[0060] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0061] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...

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Abstract

The invention discloses a preparation method of a deep trench isolation structure and a semiconductor device. The device comprises the deep trench isolation structure. According to the invention, in the preparation process of the LDMOS device, after a first trench corresponding to the deep trench isolation structure is formed by etching, phosphorus ion implantation is carried out on the first groove; an N-type heavily doped layer is forme on on the side wall and the bottom of the first trench, the N-type heavily-doped layer can lead out the N-type buried region in contact with the N-type heavily-doped layer, so that the deep N-type well does not need to be diffused to be in contact with the N-type buried layer to facilitate lead-out by consuming long time to carry out high-temperature thermal propulsion when the deep N-type well is formed, the processing time of high-temperature thermal propulsion is shortened, and the manufacturing cost is reduced; meanwhile, due to the fact that thehigh-temperature thermal propulsion time is shortened, upward further diffusion of the N-type buried layer is prevented, the withstand voltage length in the longitudinal structure of the device is increased, and the longitudinal withstand voltage is improved.

Description

technical field [0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a method for preparing a deep trench isolation (Deep Trench Isolation, DTI) structure and a semiconductor device. Background technique [0002] As the application voltage of Lateral Double-diffused Metal-Oxide Semiconductor (LDMOS) devices continues to increase, higher requirements are placed on the withstand voltage capability of the isolation structure between high-voltage devices and low-voltage devices. . The isolation structure of the PN junction (Positive Negative Junction) is widely used in the low-voltage BCD (Bipolar-CMOS-DMOS) process, but the size of the PN junction isolation structure increases sharply with the rise of the withstand voltage, and the leakage of the PN junction isolation also increases. It rises accordingly. Therefore, in order to reduce the size of the isolation structure and reduce the leakage effect, the deep trench is...

Claims

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Application Information

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IPC IPC(8): H01L21/762H01L29/06H01L29/78
CPCH01L21/76224H01L21/76237H01L29/0603H01L29/0611H01L29/0649H01L29/7816
Inventor 许昭昭
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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