FPGA-based Yolov3 network computing acceleration system and acceleration method thereof

A technology for accelerating systems and networks, applied in computing, energy-saving computing, computer components and other directions, can solve the problems of difficult to deploy embedded terminals, large amount of calculation, etc., to achieve the effect of increasing bandwidth, getting rid of bandwidth limitations, and improving detection speed

Active Publication Date: 2020-07-14
HARBIN INST OF TECH
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AI Technical Summary

Problems solved by technology

However, YOLOv3 has a large amount of calculation and is difficult to deploy on the embedded side, and the current hardware accelerator lacks a system design solution for YOLOv3 network acceleration

Method used

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  • FPGA-based Yolov3 network computing acceleration system and acceleration method thereof

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specific Embodiment 1

[0056] according to figure 1 Shown, a kind of Yolov3 network computing acceleration system based on FPGA, described system comprises ARM and FPGA platform framework, off-chip memory area, AXI_M interface and AXI_S interface, described ARM platform framework comprises core processor and data and memory controller , the FPGA platform architecture includes an acceleration core unit, an input buffer end and an output buffer end;

[0057] The core processor includes an ARM Cortex-A53CPU and an L2 cache area, the off-chip storage area includes an SD card and external DDR4, and the acceleration core unit includes a data matrix vector array and a computing module;

[0058] The ARM Cortex-A53CPU is connected to the L2 cache area, the L2 cache area is connected to the data and the memory controller, the data and the memory controller are connected to the off-chip storage area, the data and the memory controller AXI_M interface and the AXI_S interface, the The AXI_S interface is connect...

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Abstract

The invention relates to a Yolov3 network computing acceleration system based on an FPGA and an acceleration method thereof. The system comprises an ARM and FPGA platform architecture, an off-chip storage area, an AXI_M interface and an AXI_S interface, the ARM platform architecture comprises a core processor and a data and memory controller, and the FPGA platform architecture comprises an acceleration core unit, an input cache end and an output cache end; and the core processor comprises an ARM Cortex-A53 CPU and an L2 cache region, the off-chip storage region comprises an SD card and an external DDR4, and the acceleration core unit comprises a data matrix vector array and a calculation module. The input cache end and the output cache end adopt a multi-channel parallel reading and writing-back mode to replace a traditional single-channel reading and writing mode, and the bandwidth of the Zynq chip is utilized to the maximum extent. Double cache regions and a register array are designed at the input cache end, efficient data multiplexing is achieved, and the bandwidth is multiplied.

Description

technical field [0001] The invention relates to the technical field of Yolov3 network computing acceleration, and relates to an FPGA-based Yolov3 network computing acceleration system and an acceleration method thereof. Background technique [0002] As a new generation of computing model, deep learning has played an important role in many fields in recent years. Deep learning algorithms represented by convolutional neural networks have made major breakthroughs in the field of computer vision, such as image classification, object detection and other specific applications. With the advent of the Internet of Things era and the rise of edge computing, the development trend of the future society is the interconnection of everything and the perception of everything. Therefore, it is of great practical significance to deploy deep learning algorithms on the embedded side. [0003] Deep learning algorithms are characterized by intensive computing and storage, and consume a lot of co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06N3/08G06K9/62
CPCG06N3/08G06N3/045G06F18/25Y02D10/00
Inventor 郑浩然李君宝刘环宇吴然吴瑞东赵菲刘小龙
Owner HARBIN INST OF TECH
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