A yolov3 network computing acceleration system based on fpga and its acceleration method

A network and computing module technology, which is applied to the FPGA-based Yolov3 network computing acceleration system and its acceleration field, can solve the problems of difficult deployment of embedded terminals, large amount of calculation, etc., to improve bandwidth, get rid of bandwidth restrictions, and efficiently reuse data Effect

Active Publication Date: 2022-07-12
HARBIN INST OF TECH
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  • Application Information

AI Technical Summary

Problems solved by technology

However, YOLOv3 has a large amount of calculation and is difficult to deploy on the embedded side, and the current hardware accelerator lacks a system design solution for YOLOv3 network acceleration

Method used

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  • A yolov3 network computing acceleration system based on fpga and its acceleration method
  • A yolov3 network computing acceleration system based on fpga and its acceleration method
  • A yolov3 network computing acceleration system based on fpga and its acceleration method

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specific Embodiment 1

[0055] according to figure 1 As shown, a Yolov3 network computing acceleration system based on FPGA, the system includes ARM and FPGA platform architecture, off-chip storage area, AXI_M interface and AXI_S interface, and the ARM platform architecture includes a core processor and a data and memory controller , the FPGA platform architecture includes an acceleration core unit, an input cache end and an output cache end;

[0056] The core processor includes an ARM Cortex-A53CPU and an L2 cache area, the off-chip storage area includes an SD card and an external DDR4, and the acceleration core unit includes a data matrix vector array and a computing module;

[0057] The ARM Cortex-A53CPU is connected to the L2 cache area, the L2 cache area is connected to the data and the memory controller, the data and the memory controller are connected to the off-chip storage area, the data and the memory controller AXI_M interface and AXI_S interface, so The AXI_S interface is connected to th...

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Abstract

The invention is an FPGA-based Yolov3 network computing acceleration system and an acceleration method thereof. The system includes an ARM and FPGA platform architecture, an off-chip storage area, an AXI_M interface and an AXI_S interface, the ARM platform architecture includes a core processor and a data and memory controller, and the FPGA platform architecture includes an acceleration core unit, an input buffer end and an output cache end; the core processor includes an ARM Cortex-A53 CPU and an L2 cache area, the off-chip storage area includes an SD card and an external DDR4, and the acceleration core unit includes a data matrix vector array and a computing module. The input and output cache ends of the present invention use multi-channel parallel read and write back methods to replace the traditional single-channel read and write methods, and maximize the utilization of the bandwidth of the Zynq chip. The input buffer side is designed with double buffer area and register array to achieve efficient data multiplexing and double the bandwidth.

Description

technical field [0001] The invention relates to the technical field of Yolov3 network computing acceleration, and is an FPGA-based Yolov3 network computing acceleration system and an acceleration method thereof. Background technique [0002] As a new generation computing model, deep learning has played an important role in many fields in recent years. Deep learning algorithms represented by convolutional neural networks have made major breakthroughs in the field of computer vision, such as image classification, target detection and other specific applications. With the advent of the Internet of Things era and the rise of edge computing, the development trend of the future society is the interconnection of all things and the perception of all things. Therefore, it is of great practical significance to deploy deep learning algorithms on the embedded side. [0003] Deep learning algorithms are characterized by being computationally intensive and storage-intensive, and need to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/04G06N3/08G06K9/62
CPCG06N3/08G06N3/045G06F18/25Y02D10/00
Inventor 郑浩然李君宝刘环宇吴然吴瑞东赵菲刘小龙
Owner HARBIN INST OF TECH
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