Internet bus unit, data transmission method, wishbone Internet module and chip

Abstract

The invention provides an internet bus unit, a data transmission method, a wishbone Internet module and a chip. The internet bus unit comprises a cache unit, a selection unit, a processing unit and acontrol unit. The cache unit is used for caching host transmission request data output by a request output end of a host under the control of a clock signal; the selection unit is used for connectingone of the first transmission path and the second transmission path according to the cache state of the cache unit and a first response signal output by an arbitration circuit in the wishbone internetmodule; the processing unit is used for outputting a second response signal to the host according to the cache state of the cache unit and the first response signal; and the control unit is used fordetermining whether to control the cache data in the cache unit to remain unchanged or not according to the cache state of the cache unit and the first response signal. According to the invention, a better bus utilization rate can be realized, and higher clock signal frequency can be realized.

Description

technical field [0001] The invention relates to the technical field of SOC (system on a chip), in particular to an Internet bus unit and a data transmission method, a wishbone Internet module and a chip. Background technique [0002] The wishbone bus protocol was first proposed by Silicore, and is currently maintained by the OpenCores organization. The advantages of Wishbone are that it is open, free, and has many free IP cores, and it is simple, flexible, and lightweight, and is especially suitable for small The interconnection between IPs, the wishbone bus protocol supports point-to-point, shared bus, crossbar (Crossbar) and interconnection based on switch fabric (Switch fabric), the Wishbone bus specification is a "lightweight (Lightweight)" specification, it actually It focuses more on point-to-point interconnection and low-complexity shared bus system-on-chip interconnection, which supports typical data operations, including: single read / write operations, block read / wri...

AI Technical Summary

Problems solved by technology

In the process of one transmission, since the address of the slave response does not depend on the ACK_I signal, there is no feedback loop in the process of burst transmission, but the switching between two transmissions still depends on the ACK_I signal, in order to isolate the feedback from the slave The loop needs to insert a gap at the end of each transmission, which leads to low bus utilization during fragmented access

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