Inline ecc function for system-on-chip

Abstract

An example integrated circuit (IC) includes a network-on-chip (NoC) (106), a master device (302) coupled to the NoC, a memory controller (304) coupled to the NoC configured to control a memory coupledto the IC, and an inline error-correcting code (ECC) circuit (112) coupled to the NoC. The ECC circuit is configured to receive read and write transactions from the master device that target the memory, compute ECC data based on the read and write transactions, and provide outgoing transactions to the memory controller.

Description

technical field [0001] Examples of the present disclosure relate generally to electronic circuits, and in particular, to in-line error correction code (ECC) functionality for a system on chip (SoC). Background technique [0002] Traditionally, error correcting code (ECC) protection for dynamic random access memory (DRAM) has been implemented using additional "out-of-band" data bits (eg, 64 bits of data plus 8 bits of parity). This approach is costly due to the need for one or more DRAM components and additional interface input / output (IO) pins to store the ECC data. [0003] Additionally, bus structures have been found to be unsuitable for some system-on-chip (SoC) integrated circuits (SoCs). As circuit integration increases, transactions can become blocked, and increased capacity can create signaling problems. Instead of a bus structure, a network on chip (NoC) can be used to support data communication between components of the SoC. [0004] A NoC typically includes a co...

AI Technical Summary

Problems solved by technology

This approach is costly due to the need for one or more DRAM components to store ECC data and additional interface input / output (IO) pins

[0003] Additionally, the bus structure has been found to be unsuitable for some system-on-chip (SoC) integrated circuits (SoC)

As circuit integration increases, transactions can become blocked, and increased capacity can create signaling issues

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