Array substrate, preparation method and display device
An array substrate and the same technology are applied in the fields of array substrates, preparation methods and display devices, and can solve the problems of large overall thickness of pixel circuits, increased process difficulty, large depth of etching holes of polysilicon transistors, etc., so as to reduce leakage current and reduce Process difficulty, the effect of reducing the overall thickness
Active Publication Date: 2020-08-28
XIAMEN TIANMA MICRO ELECTRONICS
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Problems solved by technology
The inventors have found that at present, when preparing the pixel circuit, the polysilicon transistor is prepared first, and then the metal oxide transistor is prepared, which results in a larger overall thickness of the pixel circuit and a larger depth of the etching hole in the active layer of the polysilicon transistor, and further Increase the difficulty of the process
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[0041] In addition, the present invention also provides a method for preparing the above-mentioned array substrate, including:
[0042] providing a substrate;
[0043] At least one first polysilicon island and at least one second polysilicon island are formed on one side of the substrate, and grooves are opened on the first polysilicon island;
[0044] blocking the second polysilicon island, and performing ion implantation on the first polysilicon island to form a P-type semiconductor;
[0045] blocking the channels of the second polysilicon island and the first polysilicon island, and performing ion implantation on the source and drain electrodes of the first polysilicon island to form an N-type semiconductor;
[0046] Metal oxide is filled in the groove of the first polysilicon island.
[0047] Through the above steps, the first thin film transistor whose active layer includes polysilicon and metal oxide arranged in the same layer can be prepared, so that in the pixel circ...
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The invention provides an array substrate, a preparation method and a display device. In the array substrate, an active layer of a first thin film transistor comprises polycrystalline silicon and metal oxide which are arranged on the same layer, and the projection of the metal oxide on a substrate is located in the projection of the polycrystalline silicon on the substrate. According to the invention, the first thin film transistor adopts the metal oxide as a channel, and the electron mobility of the metal oxide is higher than that of the channel of the polycrystalline silicon transistor, so that the leakage current of the first thin film transistor can be reduced. In addition, the metal oxide and the polycrystalline silicon are arranged on the same layer, so that the active layer of the polycrystalline silicon transistor and the active layer of the first thin film transistor can be prepared by adopting the same process, the depth of an active layer etching hole of the polycrystallinesilicon transistor is the same as that of an active layer etching hole of the first thin film transistor at the moment, so that the overall thickness of a pixel circuit is reduced, and the active layer etching hole of the polycrystalline silicon transistor does not need to adopt an additional deep hole etching process.
Description
technical field [0001] The present invention relates to the field of display technology, and more specifically, to an array substrate, a manufacturing method and a display device. Background technique [0002] A hybrid transistor pixel circuit (Hybrid TFT) means that the transistors in the pixel circuit include both polysilicon transistors and metal oxide transistors. The inventors have found that at present, when preparing the pixel circuit, the polysilicon transistor is prepared first, and then the metal oxide transistor is prepared, which results in a larger overall thickness of the pixel circuit and a larger depth of the etching hole in the active layer of the polysilicon transistor, and further Increase the difficulty of the process. [0003] Therefore, how to provide an array substrate that can reduce the film thickness of the hybrid transistor pixel circuit, thereby reducing the difficulty of the etching hole process, is a major technical problem to be solved urgentl...
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Patent Timeline
Login to View More IPC IPC(8): H01L27/12H01L29/10H01L29/786H01L21/77
CPCH01L27/1222H01L27/1225H01L27/127H01L29/78696H01L29/1054
Inventor 谢锋
Owner XIAMEN TIANMA MICRO ELECTRONICS