Semiconductor structure and packaging method of chip
A packaging method and semiconductor technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of chip difficulty, chip area and cost increase, and achieve the effect of simple preparation process
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Embodiment 1
[0062] Figure 1a and Figure 1b A schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention, wherein, Figure 1b for Figure 1a A schematic cross-sectional view along the direction A-A'.
[0063] combine Figure 1a and Figure 1b As shown, the semiconductor structure includes a chip 100 and a conductive sacrificial pattern 200. The chip 100 has an electrical connection surface. On the one hand, the conductive sacrificial pattern 200 is disposed on the electrical connection surface and covers at least part of the electrical connection surface.
[0064] The electrical connection surface of the chip 100 is, for example, the front side of the chip 100 (that is, Figure 1a and Figure 1b the upper surface of the middle chip 100), but not limited thereto.
[0065] The chip 100 may be a CIS chip, a MEMS chip or a BIOS chip, etc., or any chip that requires ESD protection, and will not be illustrated here one by one.
[0066] The...
Embodiment 2
[0106] The difference between this embodiment and the first embodiment is that the conductive sacrificial pattern 200 is not an integral structure, but includes at least two (for example, 5) first patterns electrically isolated from each other.
[0107] Figure 5 A schematic structural diagram of the semiconductor structure provided in this embodiment. combine Figure 5 As shown, the conductive sacrificial pattern 200 includes first patterns 200a, 200b, 200c, 200d, 200e. Wherein, the first pattern 200a is a T-shaped structure, and its three ends respectively cover part of the top surfaces of the lead-out ends a1, d2, b2 and are electrically connected to the lead-out ends a1, d2, b2, so that the lead-out ends are connected by the first pattern 200a. a1, d2, and b2 are short-circuited; the first pattern 200b is also a T-shaped structure, and its three ends respectively cover part of the top surface of the lead-out ends d2, b2, and c2 and are electrically connected to the lead-ou...
Embodiment 3
[0113] Figure 6a and Figure 6b A schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention, wherein, Figure 6b for Figure 6a A schematic cross-sectional view along the direction A-A'.
[0114] combine Figure 6a and Figure 6b As shown, the difference between this embodiment and Embodiment 1 and Embodiment 2 is that a conductive pattern 300 is also formed in the chip 100, the top surface of the conductive pattern 300 is completely exposed to the surface of the chip 100, and the There is a gap between the conductive pattern 300 and the lead-out end, the conductive sacrificial pattern 200 is at least located on the gap, and extends to cover at least part of the top surface of the lead-out end and at least part of the top surface of the conductive pattern 300, through The conductive sacrificial pattern 200 electrically connects the conductive pattern 300 to the lead end.
[0115] It should be understood that the top sur...
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Abstract
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