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Memory and forming method thereof

A memory and bit line technology, applied in semiconductor devices, electrical solid state devices, semiconductor/solid state device manufacturing, etc., can solve problems affecting memory performance and abnormal appearance, so as to improve appearance accuracy, ensure appearance, and improve graphics The effect of precision

Active Publication Date: 2020-09-08
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a memory to solve the problem that the bit line and node contact at the edge of the existing memory are prone to abnormal morphology, thereby affecting the performance of the memory

Method used

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  • Memory and forming method thereof
  • Memory and forming method thereof
  • Memory and forming method thereof

Examples

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Embodiment 2

[0152] The difference from Embodiment 1 is that in this embodiment, a third contact portion and a fourth contact portion are further provided in the peripheral area. Figure 5 It is a schematic cross-sectional view of the memory in Embodiment 2 of the present invention, such as Figure 5 As shown, the third contact portion 430 includes an insulating pillar 430a and a third electrically conductive layer 430b, and the third electrically conductive layer 430b covers the top surface of the insulating pillar 430a. And, the fourth contact portion 440 only includes insulating pillars.

[0153] Further, the fourth contact portion 440 and the third contact portion 430 are arranged alternately in sequence, and the insulating column 430a of the third contact portion 430 and the insulating column of the fourth contact portion 440 are filled with isolation Material. In this embodiment, there is a fourth contact portion 440 between the third contact portion 430 closest to the memory area ...

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PUM

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Abstract

The invention provides a memory and a forming method thereof. The width of a first bit line located at an edge position in a bit line group is greater than the width of a second bit line arranged in the bit line group, so that when the bit line group is prepared, the morphology of the first bit line can be guaranteed, and the morphology precision of the second bit line can be improved under the blocking protection of the first bit line with larger width, thereby being beneficial to improving the device performance of the formed memory. Similarly, as the width of the first contact part locatedat the edge position in the plurality of node contact parts is larger than that of the second contact part, the morphology of the first contact part can be correspondingly ensured, the pattern precision of the second contact part is improved, and the device performance of the formed memory is further improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof. Background technique [0002] A memory, such as a dynamic random access memory (DRAM), generally has a memory cell array, and the memory cell array includes a plurality of memory cells arranged in an array. And, the memory also has a plurality of bit lines, each of which is electrically connected to a corresponding memory unit, and the memory also includes a storage capacitor for storing charges representing stored information, and the The storage unit can be electrically connected to the storage capacitor through a node contact, so as to realize the storage function of each storage unit. [0003] At present, a method for forming a memory generally includes: forming a bit line group, and using the bit line group to define a node contact window, and then filling the node contact window with a conductive material to form a node contact...

Claims

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Application Information

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IPC IPC(8): H01L27/108H01L21/768H01L23/528H01L21/8242
CPCH10B12/312H10B12/30
Inventor 赖惠先林昭维朱家仪童宇诚吕前宏
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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