Configuration system and method of field programmable logic gate array

Abstract

The invention relates to the technical field of field programmable logic gate arrays, in particular to a configuration system and method of a field programmable logic gate array, and the system comprises an NAND memory and an FPGA; the NAND memory comprises a data array, a code matching array, a first configuration interface and an NAND controller; the FPGA comprises a second configuration interface and an NAND interface, the second configuration interface is connected with the first configuration interface, and the NAND interface is connected with the NAND controller. According to the invention, the code matching file and the access data are stored in the NAND memory together, so that the integration of configuration and storage of the FPGA is achieved, the whole system only needs one external memory, the expenditure of an independent FPGA configuration memory circuit is saved, the board-level area is saved, and the board-level development difficulty is reduced. Meanwhile, due to thelarge-capacity characteristic of the NAND memory, multiple configuration versions can be stored for the FPGA, and the configuration flexibility of the FPGA is improved.

Description

technical field [0001] The invention relates to the technical field of field programmable logic gate arrays, in particular to a configuration system and method for field programmable logic gate arrays. Background technique [0002] Field Programmable Gate Array (Field Programmable GateArray, FPGA) as a flexible and configurable device, with the development of information industry and microelectronics, is more and more used in video image processing, communication field, digital signal processing and other fields, and requires FPGA has multiple functions and stronger data processing capabilities. [0003] Traditional FPGA systems need to be connected with configuration memory and data memory for use together. Its structure is as figure 1 As shown, the configuration memory generally adopts NOR memory, which is used to store the FPGA configuration code. After power-on, the configuration code is transmitted to the FPGA to complete the power-on configuration. The data memory g...

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Problems solved by technology

[0006] The purpose of the present invention is to provide the configuration system and method of Field Programmable Logic Gate Array, to solve the technical problem of needing to store FPGA configuration file by NOR memorizer in the prior art

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