Dual-core system clock synchronization method and device based on timestamp marking circuit

Abstract

The invention discloses a dual-core system clock synchronization method and device based on a timestamp marking circuit. The method is characterized in that the timestamp-based marking circuit comprises a local clock unit, a frequency compensation register, a synchronous message / and delay request detection circuit, a synchronous message / delay request time latch, a first base address data register,a second base address data register and a time event state register, firstly, a CPU writes a frequency compensation value into a frequency compensation register through a bus interface, and a local clock unit is started to serve as a local clock reference; writing an address of a second base address data register into the first base address data register, and writing an address of the first baseaddress data register into the second base address data register. The method and the device have the advantages that the timestamp is obtained by the hardware circuit at the bottom layer, the slave clock can quickly calculate and adjust the deviation with the master clock according to the transceiving timestamp, and master-slave clock synchronization is completed.

Description

technical field [0001] The invention relates to the field of clock synchronization between an AIRT-ROS real-time system and a non-real-time system, and more particularly relates to a dual-core system clock synchronization method and device based on a time stamp marking circuit. Background technique [0002] At present, the application scenarios of most clock synchronization algorithms are clock synchronization in an Ethernet environment. For example, Chinese Patent Publication No. CN103067112A discloses a clock synchronization method, device and network equipment. The device includes: at least one hardware chip, CPU and logic control Chip; the hardware chip is used to receive the first PTP event message sent by the peer device, record the first time stamp, subtract the first time stamp from the correction value in the CF field of the first PTP event message, and then send it to the CPU ; The CPU is used to send the first PTP event message to the logic control chip; the logic...

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Problems solved by technology

[0003] The network delay in the Ethernet environment is one of the main factors to be considered by the clock synchronization algorithm. Since the delay of the Ethernet may reach 50ms, it has a great impact on the accuracy of the clock synchronization, and the delay will be different due to the different loads in the network. big jitter

Therefore, the clock synchronization algorithm in Ethernet is not suitable for clock synchronization of dual-core dual systems

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