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Silicon carbide UMOSFET device integrated with JBS

A silicon carbide and device technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problem of weak internal freewheeling capability of silicon carbide UMOSFET devices, increasing the complexity and cost of circuit systems, and incapable of device freewheeling. and other problems, to achieve the effect of improving breakdown characteristics, reducing manufacturing costs, and improving freewheeling capability.

Active Publication Date: 2020-10-09
芜湖西晶微电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the large bandgap of silicon carbide materials, the turn-on voltage of the parasitic PiN diodes integrated in silicon carbide UMOSFET devices is mostly around 3V, which cannot provide freewheeling for the device itself, resulting in the internal freewheeling capability of silicon carbide UMOSFET devices. weaker
Therefore, in power electronic system applications such as full bridges, an additional Schottky diode is often used in antiparallel as a freewheeling diode, which greatly increases the complexity and cost of the circuit system.
In addition, in the blocking mode, a series of reliability problems will be caused due to the strong electric field of the gate oxide at the corner of the trench

Method used

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  • Silicon carbide UMOSFET device integrated with JBS
  • Silicon carbide UMOSFET device integrated with JBS
  • Silicon carbide UMOSFET device integrated with JBS

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0034] See figure 1 , figure 1 It is a schematic structural diagram of a silicon carbide UMOSFET device integrating JBS (Junction Barrierschottky, Junction Barrier Schottky) provided by an embodiment of the present invention. As shown in the figure, the silicon carbide UMOSFET device integrating JBS in the embodiment of the present invention includes:

[0035] N+ substrate region 1;

[0036] The N- epitaxial region 2 is arranged on the N+ substrate region 1;

[0037] The P-well region 3 is arranged on the N-epitaxial region 2;

[0038] The N+ injection region 4 is arranged on the P-well region 3;

[0039] The first P+ implantation region 5 is located inside the N- epitaxial region 2;

[0040] The second P+ implantation region 6 is located inside the N- epitaxial region 2 and is spaced apart from the first P+ implantation region 5;

[0041] The gate is arranged adjacent to the P-well region 3 and the N+ implantation region 4, and is partially located inside the N-epitaxy ...

Embodiment 2

[0059] See Figure 2a-Figure 2h , Figure 2a-Figure 2h It is a process schematic diagram of a silicon carbide UMOSFET device integrating JBS provided by an embodiment of the present invention, and the preparation method includes the following steps:

[0060] Step a: Form N- epitaxial region 2 on N+ substrate region 1 by means of epitaxial growth, such as Figure 2a shown.

[0061] First, the thickness is 350 μm, and the doping concentration is 5×10 18 cm -3 The SiC substrate was cleaned by RCA standard, and then epitaxially grown on the N+ substrate region 1 with a thickness of 10 μm and a doping concentration of 6×10 15 cm -3 N-Epi region 2.

[0062] Step b: Perform well implantation on the upper surface of the N- epitaxial region 2 to form a P-well region 3, and perform N ion implantation in the P-well region 3 to form an N+ implantation region 4, such as Figure 2b shown.

[0063] Deposit and form a mask layer on the N-epitaxial region 2, form a mask pattern by phot...

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Abstract

The invention relates to a silicon carbide UMOSFET device integrated with JBS. The device comprises an N+ substrate region, an N- epitaxial region, a P-well region, an N+ injection region, first P+ injection regions, second P+ injection regions, a grid electrode, a source electrode and a drain electrode, wherein the depth of the grid electrode is smaller than the depths of the first P+ injection regions, the second P+ injection regions and the first P+ injection regions are arranged at intervals and are consistent in depth, the interface of the source electrode and the P-well region, the interface of the N+ injection region, the interfaces of the first P+ injection regions and the interfaces of the second P+ injection regions are in ohmic contact, and the interface of the source electrodeand the N- epitaxial region is Schottky contact. According to the silicon carbide UMOSFET device integrated with the JBS, P+ injection is carried out on the surface of the thin N- epitaxial region formed through etching, so that the depths of the P+ injection regions are larger, and the breakdown characteristic of the device can be further improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a silicon carbide UMOSFET device integrating JBS. Background technique [0002] In recent years, with the continuous development of power electronic systems, higher requirements have been placed on the power devices in the system. Silicon (Si)-based power electronic devices have been unable to meet the requirements of system applications due to the limitations of the material itself. As a representative of the third-generation semiconductor material, silicon carbide (SiC) materials are far better than silicon materials in many characteristics. Silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor) device, as a commercialized device in recent years, has an alternative in terms of on-resistance, switching time, switching loss and heat dissipation performance. The huge potential of the existin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/06H01L29/16H01L29/423
CPCH01L29/0603H01L29/0684H01L29/1608H01L29/4236H01L29/66068H01L29/7827H01L29/7839
Inventor 汤晓燕余意袁昊何艳静宋庆文张玉明
Owner 芜湖西晶微电子科技有限公司
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