Three-dimensional integrated circuit layout method based on graphic processing

Abstract

The invention discloses a three-dimensional integrated circuit layout method based on graphic processing, and the three-dimensional integrated circuit layout method comprises the steps: carrying out layout operation of a three-dimensional integrated circuit layout through an image processor, wherein the layout operation comprises the steps: global layout, legalization and detailed layout; enteringglobal layout at the beginning of initial layout, and overlapping a large number of modules of the layout to form a layout with very high density and very short line length; changing the positions ofthe modules in the layout through a plurality of layout engines, reducing the overlapping degree between the modules, and finally achieving a layout result meeting conditions; after the global layoutis finished, legalizing the whole layout, and emptying the residual overlapping; and carrying out layout optimization through detailed layout. The three-dimensional integrated circuit layout algorithm research is simplified, and the time consumed in the circuit layout process is shortened, and the layout result is optimized, and the manufacturing efficiency of the chip is improved.

Description

technical field [0001] The invention belongs to the technical field of circuit layout, in particular to a three-dimensional integrated circuit layout method based on graphic processing. Background technique [0002] Three-dimensional integrated circuits are one of the ideal solutions to overcome the high complexity and high interconnectivity of modern and next-generation integrated circuits. At the same time, three-dimensional integrated circuits can effectively reduce the length of interconnection lines and improve circuit performance. Layout is a critical but time-consuming process in the physical design of integrated circuits. It determines the position of each cell in the layout, and its layout results also have a huge impact on subsequent work. It is also valuable for early logic synthesis because a placement result usually yields a relatively accurate routing line length and routing congestion. Existing layout methods usually use multiple layout engines for layout c...

AI Technical Summary

Problems solved by technology

Some people also proposed to use GPU to accelerate line length gradient calculation and area calculation, but their experiments lacked consideration of real constraints, such as density constraints

In addition, most of the current research is to accelerate two-dimensional layout, and there is little work on accelerating three-dimensional layout.

At the same time, the lack of a public framework results in high development costs and raises the threshold for verifying new algorithms

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