Neural network computing system and method based on data flow architecture

Abstract

The embodiment of the invention discloses a neural network computing system and method based on a data flow architecture. The neural network computing system based on the data flow architecture comprises an off-chip memory and a neural network acceleration module, wherein the neural network acceleration module comprises a conversion unit, an on-chip memory and a computing unit; the off-chip memoryis used for storing data; the conversion unit is connected between the on-chip memory and the off-chip memory and is used for realizing conversion between a first communication bus of the off-chip memory and a second communication bus of the on-chip memory so as to store the data into the on-chip memory; and the calculation unit is directly connected with the on-chip memory through a second communication bus and is used for performing calculation based on the data received from the on-chip memory. The conversion unit is arranged between the on-chip memory and the off-chip memory, so the speedand the efficiency of neural network calculation of the data flow architecture are improved under the condition of ensuring the cost.

Description

technical field [0001] The embodiments of the present application relate to the technical field of neural networks, for example, a neural network computing system and method based on a data flow architecture. Background technique [0002] With the rapid development of computers, the calculation of neural network data is becoming more and more important. Neural network calculations require large amounts of data. The data flow architecture completes the entire computing process based on the continuous flow of data, without the participation of instruction sets. The traditional instruction set architecture needs to go through several stages to complete a complete operation. The instruction fetch stage, the instruction decoding stage, the instruction execution stage, the memory access stage, and the result write-back stage. The whole process is extremely inefficient. Compared with the instruction set architecture, the data flow architecture can maximize the performance and eff...

AI Technical Summary

Problems solved by technology

[0004] However, although the cost of method 1 is relatively low, the transmission rate is limited by the speed and bandwidth of the bus

Because often a chip will have multiple devices accessing external storage at the same time, and the external storage can only be read or written at the same time, and reading and writing cannot be done at the same time

This seriously affects the data transmission efficiency, and the neural network must receive the data before it can start calculations, so the data transmission time and data processing time of method 1 are difficult to overlap, resulting in performance bottlenecks

Method 2 Although local storage saves the transmission time of a piece of data, the capacity of the local storage must be greater than the layer with the largest amount of data in the neural network to achieve full functionality, which will result in a large area of ​​the chip, resulting in The cost of chips has risen sharply

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