A Chip Clamping and Fixing and Chip Parallelism Measuring Structure for Ultrasonic Bonding

Abstract

The invention discloses a chip clamping and fixing and chip parallelism measuring structure for ultrasonic bonding, comprising a long-pin chip parallelism measuring structure close to a suction nozzle and a short-pin chip clamp outside the long-pin chip parallelism measuring structure maintain a fixed structure. According to the principle of the sliding rheostat, the invention can accurately read the offset of chip parallelism by measuring the resistance change caused by the position change of the long pins, and through the determination formula of resistance, so as to realize accurate chip parallelism measurement and solve the problem of When the suction nozzle is parallel to the substrate, there may be external factors such as non-parallel chips caused by the height of the electrical contact bumps. In addition, during the ultrasonic bonding process of the short pins, the unfolded part can fix the position of the chip, thereby protecting the chip and increasing the bonding efficiency.

Description

technical field [0001] The invention belongs to the technical field of chip bonding and packaging, and in particular relates to a chip clamping and fixing and chip parallelism measuring structure. Background technique [0002] Chip interconnection technology affects the volume, performance and cost of microelectronic products. The commonly used chip interconnection technologies include wire bonding, automatic tape welding and flip chip bonding. Among these technologies, the wire bonding technology has the highest market share. Although the wire bonding process is simple and low in cost, there are some disadvantages, especially with the development of miniaturization and light weight of RF module products, chips The number of pins increases, and the I / O leads using wire bonding technology are arranged around the chip, and wire bonding will lead to an increasing volume. However, with flip-chip technology, the I / O leads can be arranged on the surface of the chip in an array, s...

AI Technical Summary

Problems solved by technology

If the flip chip is not parallel to the substrate during the bonding process, it will greatly affect the bonding quality and the coupling between the chip and the substrate; If the back connection is unstable, the relative displacement between the suction nozzle and the back of the chip will occur during the bonding process, which will wear the back of the chip and affect the final performance of the device. It may also cause the chip to be damaged or even worn out, resulting in the prepared device becoming a waste product , reducing the bonding efficiency

[0005] In order to prevent the occurrence of non-parallel between the chip and the substrate or the relative displacement between the nozzle and the chip during the ultrasonic bonding process, it is necessary for the nozzle to have high requirements on the fixing ability of the chip, and at the same time, there must be a certain degree of parallelism between the chip and the substrate. High requirements, the relative displacement between the nozzle and the chip can be prevented to a certain extent by using a large negative pressure nozzle, but it is difficult to control the relative displacement within a certain degree when facing different ultrasonic energy inputs. At the same time, the measurement of the parallelism between the chip and the substrate needs to be accurate and simple, so as to achieve accurate and fast parallelism adjustment during the bonding process

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