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Sealing ring structure of a semiconductor wafer and preparation method thereof

A semiconductor and sealing ring technology, which is applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve the problems of not being able to protect semiconductor chips well, chip collapse, chip edge damage, etc., to block water vapor Penetration, good water vapor penetration, simple and easy production method

Active Publication Date: 2022-01-07
ZHANGJIAGANG SHANMU NEW MATERIAL TECH DEV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

During the process of cutting the chip, the stress generated by the dicing knife will cause damage to the edge of the chip, and even cause the chip to collapse
Currently, in order to prevent the chip from being damaged during cutting, a sealing ring is provided around the active device area of ​​the chip. The sealing ring can block the stress generated by the dicing knife and cause unwanted stress cracking in the active device area, and the chip sealing ring can prevent Chemical damage caused by water vapor penetration such as acid-containing substances, alkali-containing substances or diffusion of pollution sources, but current sealing rings cannot protect semiconductor chips well

Method used

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  • Sealing ring structure of a semiconductor wafer and preparation method thereof
  • Sealing ring structure of a semiconductor wafer and preparation method thereof
  • Sealing ring structure of a semiconductor wafer and preparation method thereof

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Embodiment Construction

[0023] In order to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0024] It should be clear that the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0025] Terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. As used in the embodiments of the present invention and the appended claims, the singular forms "a", "said" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0026] It should be understood that the term "an...

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Abstract

The present invention relates to a sealing ring structure of a semiconductor wafer and a preparation method thereof. The method comprises the following steps: forming first grooves and second grooves arranged in parallel in the sealing ring region of a semiconductor substrate, and forming a first groove and a second groove in the first A first metal nanoparticle layer, a first dielectric layer, and a second metal nanoparticle layer are sequentially formed in the groove, a metal material is deposited in the second groove to form the first metal layer, and the a second metal nanoparticle layer outside the first groove and a first metal layer outside the second groove, then depositing a first metal / dielectric stack on the second metal nanoparticle layer, to forming a first sealing ring; and depositing a second metal / dielectric stack on the first metal layer to form a second sealing ring.

Description

technical field [0001] The invention relates to the technical field of semiconductor preparation, in particular to a sealing ring structure of a semiconductor wafer and a preparation method thereof. Background technique [0002] In the manufacturing process of a semiconductor wafer, a semiconductor chip including a semiconductor active device and an interconnection structure disposed on the device can be formed on a semiconductor substrate through processes such as photolithography, etching, and deposition. Usually, multiple chips can be formed on a wafer, and finally these chips are cut off from the wafer for packaging process to form an integrated circuit area. During the process of dicing the chip, the stress generated by the dicing knife will cause damage to the edge of the chip, and even cause the chip to collapse. Currently, in order to prevent the chip from being damaged during cutting, a sealing ring is provided around the active device area of ​​the chip. The seali...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/00H01L23/16
CPCH01L23/562H01L23/16
Inventor 沈佳慧汤亚勇苏华
Owner ZHANGJIAGANG SHANMU NEW MATERIAL TECH DEV