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Substrate for PERC battery, and PERC battery and preparation method thereof

A substrate and battery technology, applied in the field of solar cells, can solve problems such as low battery efficiency, high contact resistance, and inability to fill edge areas

Pending Publication Date: 2020-11-24
YANCHENG CANADIAN SOLAR INC +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When such a structure is printed with aluminum paste, the edge area cannot be well filled by the aluminum paste, and it is easy to produce voids after sintering (such as Figure 8 As shown), the contact resistance between the aluminum back field and the silicon substrate is large, and the battery efficiency is low, so it needs to be solved

Method used

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  • Substrate for PERC battery, and PERC battery and preparation method thereof
  • Substrate for PERC battery, and PERC battery and preparation method thereof
  • Substrate for PERC battery, and PERC battery and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0070] This embodiment provides a PERC battery, such as figure 1 , Figure 4 and Figure 5 As shown, it includes: a silicon wafer layer 1 with a PN junction, a back passivation layer 2, a protective layer 3 and a back field layer 4 arranged sequentially from the back of the silicon wafer layer 1 with a PN junction, and a back field layer 4 from the silicon wafer layer 1 with a PN junction. A front passivation layer 5 and a front electrode 6 arranged sequentially from the front side of the silicon wafer layer 1 outward;

[0071] The back passivation layer 2 and the protective layer 3 are provided with a plurality of periodically arranged grooves 7, the grooves 7 penetrate the back passivation layer 2 and the protective layer 3, and the part of the back field layer 4 located in the groove 7 is connected with the The silicon wafer layer 1 of the PN junction is connected;

[0072] The groove 7 includes a first groove area 71 and a second groove area 72 along the depth directio...

Embodiment 2

[0086]This embodiment provides a PERC battery, such as figure 2 , Figure 4 and Figure 5 As shown, it includes: a silicon wafer layer 1 with a PN junction, a back passivation layer 2, a protective layer 3 and a back field layer 4 arranged sequentially from the back of the silicon wafer layer 1 with a PN junction, and a back field layer 4 from the silicon wafer layer 1 with a PN junction. A front passivation layer 5 (consisting of a front first passivation layer 51 and a front second passivation layer 52) and a front electrode 6 are arranged sequentially from the front side of the silicon wafer layer 1 outward;

[0087] The back passivation layer 2 and the protective layer 3 are provided with a plurality of periodically arranged grooves 7, the grooves 7 penetrate the back passivation layer 2 and the protective layer 3, and the part of the back field layer 4 located in the groove 7 is connected with the The silicon wafer layer 1 of the PN junction is connected;

[0088] The...

Embodiment 3

[0102] This embodiment provides a PERC battery, such as image 3 , Figure 4 and Figure 5 As shown, it includes: a silicon wafer layer 1 with a PN junction, a back passivation layer 2, a protective layer 3, a back field layer 4 and a back electrode 8 arranged sequentially from the back of the silicon wafer layer 1 with a PN junction outward, and from A front passivation layer 5 (consisting of a front first passivation layer 51 and a front second passivation layer 52) and a front electrode 6 are sequentially arranged on the front side of the silicon wafer layer 1 having a PN junction;

[0103] The back passivation layer 2 and the protective layer 3 are provided with a plurality of periodically arranged grooves 7, the grooves 7 penetrate the back passivation layer 2 and the protective layer 3, and the part of the back field layer 4 located in the groove 7 is connected with the The silicon wafer layer 1 of the PN junction is connected;

[0104] The groove 7 includes a first g...

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Abstract

The invention provides a substrate for a PERC battery, the PERC battery and a preparation method thereof. The substrate comprises a silicon wafer layer with a PN junction, and a back passivation layerand a protective layer which are sequentially arranged outwards from the back surface of the silicon wafer layer with the PN junction; a plurality of grooves are formed in the back passivation layerand the protective layer and penetrate through the back passivation layer and the protective layer; the groove comprises a first groove area and a second groove area in the depth direction, the secondgroove area is located at the bottom of the first groove area and communicated with the first groove area, and the opening area of the first groove area is larger than that of the second groove area.The PERC cell comprises the substrate, a back surface field layer arranged on the back surface of the substrate, and a front surface passivation layer and a front surface electrode which are sequentially arranged from the front surface of the substrate to the outside. By adopting the groove with the structure on the PERC battery, the generation of cavities between the back field layer material and the silicon substrate after sintering can be effectively reduced.

Description

technical field [0001] The invention belongs to the technical field of solar cells, and in particular relates to a substrate for PERC cells, a PERC cell and a preparation method thereof. Background technique [0002] Among the existing sustainable energy sources, solar energy is undoubtedly the cleanest, most common and most potential energy source. Solar power generation devices, also known as solar cells or photovoltaic cells, can directly convert solar energy into electrical energy. The principle of power generation is based on the photovoltaic effect of semiconductor PN junctions. [0003] High efficiency and low cost are the main goals pursued by crystalline silicon solar cells at present. Partial contact back passivation (PERC) solar cells are currently the main technology to improve the performance of crystalline silicon solar cells. The core is to use aluminum oxide or A silicon oxide film (5-100 nanometers) is used to cover the surface to passivate the surface and ...

Claims

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Application Information

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IPC IPC(8): H01L31/0216H01L31/0236H01L31/068H01L31/18B23K26/364B23K26/402
CPCB23K26/40B23K26/364H01L31/02167H01L31/02366H01L31/0682H01L31/1804H01L31/1868Y02E10/547Y02P70/50
Inventor 刘志强曹琨袁中存费正洪
Owner YANCHENG CANADIAN SOLAR INC
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