ddr control system and ddr storage system

Abstract

The present invention provides a kind of DDR control system and DDR storage system, based on the SoC architecture that is integrated in the MCU core and FPGA core in the same system-on-chip, realize the connection between the MCU and the off-chip DDR memory based on the logic resources in the FPGA core. The DDR control system between the two, the DDR control system is an on-chip DDR control system, including the MCU bus mapping module, DDR data cache module and DDR controller module, and based on the programmable characteristics of FPGA, the number of DDR controller modules and the MCU The number of subsystem buses mapped by the bus mapping module can be dynamically adjusted. Users can dynamically configure the number of DDR controller modules outside the MCU, and further dynamically configure the connected off-chip DDR memory through the DDR controller module to achieve on-chip The function and data of the external DDR memory can be dynamically configured, which improves the scalability and ease of use of the MCU, and helps users quickly apply the DDR memory.

Description

technical field [0001] The invention relates to the technical field of DDR storage, in particular to a DDR control system and a DDR storage system. Background technique [0002] Double data rate (Double Data Rate, DDR) memory Compared with traditional single data rate memory, DDR memory technology realizes two read and write operations in one clock cycle, that is, it is executed on the rising edge and falling edge of the clock respectively. A read and write operation. The speed advantage of DDR memory is widely used in image processing and other fields. [0003] With the rapid development of DDR memory technology, higher requirements are put forward for the field of microcontroller (Micro Controller Unit, MCU) control, especially in the field of image processing, it is required that the MCU can directly access the DDR memory. However, there is no dedicated DDR interface in the traditional MCU single-core architecture. The MCU core needs to access its external DDR storage t...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a kind of DDR control system and DDR storage system, can realize the DDR control system on-chip based on FPGA logic resource, to solve the problem that traditional MCU must rely on external DDR control chip to read and write control DDR memory problem

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