Pixel compensation circuit, display device and pixel compensation method
A compensation circuit and pixel technology, applied in the field of communication, can solve the problem of low PPI of AMOLED display devices, and achieve the effects of simplifying the structure, reducing the occupied space, and simplifying the control logic
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Embodiment approach 1
[0026] see figure 1 and figure 2 ,in, figure 1 It is a circuit diagram of the first pixel compensation circuit provided in the embodiment of the present application; figure 2 It is a timing pulse diagram of the scan control signal and the switch control signal in the first pixel compensation circuit provided by the embodiment of the present application. Such as figure 1 As shown, the first pixel compensation circuit provided in the embodiment of the present application includes:
[0027] Light-emitting diode 1, data signal transmission end (ie figure 1 The signal transmission terminal used to transmit the data signal Vdata shown in), the high voltage transmission terminal (ie, as figure 1 The transmission terminal used to transmit the high-voltage signal Vdd shown in ), the reset signal transmission terminal (ie, as shown in figure 1 The signal transmission terminal used to transmit the reset signal Vi shown in), the scanning signal input terminal (ie, as shown in fig...
Embodiment approach 2
[0064] see image 3 and Figure 4 ,in, image 3 It is a circuit diagram of the second pixel compensation circuit provided by the embodiment of the present application; Figure 4 It is a timing pulse diagram of the scan control signal and the switch control signal in the second pixel compensation circuit provided by the embodiment of the present application.
[0065] with such figure 1 and figure 2 The first pixel compensation circuit shown differs in that, as image 3 In the pixel compensation circuit shown, T1, T5 and T6 are NMOS transistors; T2, T3 and T4 are PMOS transistors.
[0066] And in this embodiment, the Scan[n] signal and the EM[n] signal are respectively as follows Figure 4 The pulse signal shown.
[0067] Specifically, within the first frame time t1, the Scan[n] signal is at a low potential (also called a low pulse signal), and the EM[n] signal is at a high potential. At this time, under the action of the Scan[n] signal and the EM[n] signal, T3 and T4 a...
Embodiment approach 3
[0076] see Figure 5 and Figure 6 ,in, Figure 5 is a circuit diagram of the third pixel compensation circuit provided by the embodiment of the present application; Figure 6 It is the timing pulse diagram of the scan control signal and the switch control signal in the third pixel compensation circuit provided by the embodiment of the present application.
[0077] with such figure 1 and figure 2 The first pixel compensation circuit shown differs in that, as Figure 5 In the pixel compensation circuit shown, T1, T2, T3 and T4 are NMOS transistors; T5 and T6 are PMOS transistors.
[0078] And in this embodiment, the Scan[n] signal and the EM[n] signal are respectively as follows Figure 6 The pulse signal shown.
[0079] Specifically, within the first frame time t1, the Scan[n] signal is at a high potential (also called: a high pulse signal), and the EM[n] signal is at a low potential (also called: a low pulse signal) . At this time, T3 and T4 as NMOS transistors are ...
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