Device and method for dynamic partially reconfigurable configuration for remote FPGA devices

Abstract

The invention relates to a dynamic partial reconfigurable configuration device and method for remote FPGA equipment. The device includes a remote management platform and an FPGA reconfigurable system platform; the remote management platform and the FPGA reconfigurable system platform communicate through a 5G local area network; the FPGA reconfigurable system platform includes: a static The dynamic logic area and the external RAM / ROM storage unit in the logic area and FPGA; The static logic area in the FPGA is respectively connected with the dynamic logic area in the remote management platform, the external RAM / ROM storage unit and the FPGA connect. The invention reduces system power consumption and operation and maintenance costs.

Description

technical field [0001] The invention relates to the field of electrical digital data processing, in particular to a device and method for dynamic partial reconfigurable configuration oriented to remote FPGA equipment. Background technique [0002] Reconfigurable Computing (Coarse-grained Reconfigurable Architecture, CGRA) is a computing processing method with a highly flexible computing organization structure. The main difference from using ordinary microprocessors is that reconfigurable computing has the ability to make substantial changes to the data path and control flow. [0003] The concept of reconfigurable computing began in the 1960s with Gerald Estrin's iconic article. The article proposes the concept of having a standard processor and a reconfigurable hardware matrix in a computer. The main standard processor is responsible for controlling the reconfigurable hardware. Reconfigurable hardware will be customized to perform a specific job, such as image processing ...

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Problems solved by technology

[0006] When the FPGA officially enters the uninterrupted working state, if the operation and maintenance personnel find that the preset hardware modules cannot meet the new application requirements, or some reconfigurable hardware modules need to be upgraded and optimized, they need to erase and rewrite the memory on site During the maintenance period, the supporting industrial facilities had to be suspended or even stopped working, and the operation and maintenance costs were too high

[0007] In addition, many static logic areas (responsible for communication, control, and auxiliary partial reconfiguration) and dynamic logic areas inside the FPGA (responsible for the main functions of the reconfigurable system) coexist in design schemes at this stage, even if the system has been partially completed. The reconstruction work has entered a stable operation stage mainly based on the logic function of the dynamic area. At this time, the logic in the static area still works at a higher clock frequency, resulting in unnecessary waste of power consumption, and even Risk of overheating due to high frequency operation

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