Voltage drop analysis method and device compatible with IP circuit performance simulation and electronic equipment

Abstract

The embodiment of the invention discloses a voltage drop analysis method and device compatible with IP circuit performance simulation and electronic equipment, relates to the technical field of integrated circuits, and the method and the device are used for guiding circuit design optimization and reducing the influence of voltage drop on circuit performance. In the voltage drop analysis method compatible with the IP circuit performance simulation, the IP circuit performance simulation comprises the steps of setting simulation excitation, extracting a circuit netlist with parasitic parameters from a layout, writing a measurement file and performing circuit simulation. The voltage drop analysis method comprises the steps of searching an MOS transistor of which a source end or a drain end isconnected with a power line or a ground line from the circuit netlist; modifying the measurement file to increase the measurement of the voltage of the source end or the drain end of the found MOS tube; and after the circuit simulation is completed, obtaining a voltage drop result file. The method is suitable for occasions needing voltage drop analysis.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a voltage drop analysis method, device, electronic equipment and storage medium compatible with IP circuit performance simulation. Background technique [0002] The power line in the chip is a metal connection, which has resistance. When the current flows through the resistance, a voltage drop will occur, which is the so-called IR drop. If the IR drop is too large, it means that the power supply network of the chip is not strong enough, and the power supply voltage actually applied to the MOS tube will be much smaller than the ideal voltage value, which will have a great impact on the performance of the chip, so now we must The chip performs IR drop analysis to optimize the power network design of the chip. [0003] As we all know, various performance simulations are required in the circuit design process, such as timing analysis (performance), power consumption anal...

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Problems solved by technology

[0003] As we all know, various performance simulations are required in the circuit design process, such as timing analysis (performance), power consumption analysis (power), area evaluation (area, the former The three are collectively referred to as PPA analysis), signal integrity (signalintegrity, SI) verification, symmetry design of analog circuits, clock jitter (clock jitter) verification, etc., and the general EDA (Electronics Design Automation, electronic design automation) tool is the The IR drop analysis is done separately from the performance simulation of the circuit, so that it is impossible to directly obtain the impact of the IR drop on the various performances of the circuit

[0004] Specifically, totem tools are commonly used in the industry to analyze the IR drop of IP circuits (circuits with certain functions used on chips). IR drop analysis is more accurate and can be used as a sign-off standard for IR drop. However, since the totem tool and commonly used circuit simulation tools are not provided by the same EDA company, IR drop analysis and circuit simulation should be separated during the circuit design process. Doing it increases the burden of the design process, and it is impossible to directly get how much impact IR drop has on the performance of the circuit

In addition, to use totem, the tool setting is more cumbersome. Usually, after the circuit layout (layout) has been completed, totem will be used to do an IR drop analysis. At this time, if the IR drop result does not meet the requirements, go back to it. It takes a long time to modify the layout

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