A high-stability timing signal generation method and device

Abstract

The invention discloses a high-stability sequence signal generation method and device. The method includes: selecting a trigger source according to a control signal, setting a delay length and a pulse duration; using a counter to delay and store the number of delay cycles in the control data It is set and used as the first level, using the integrated feedback delay chain module and taking the half cycle of the clock source as the total length of the m-level delay of the whole chain to realize the construction of the delay path; when the trigger signal comes, it will be generated when the trigger is captured The reference signal, the main delay path starts a two-stage delay accordingly; the external trigger TDC chain measures the time difference between the trigger signal and the reference signal, and obtains the integrated feedback delay chain stages to be compensated according to the time difference; when the main delay ends, The pulse edge is sent into the compensation delay, and the signal with the internal reference as the reference delay is converted into a fixed delay signal with the original trigger as the reference, and the pulse shaking caused by the capture is eliminated through the integrated feedback delay chain to output high stability timing signal.

Description

Technical field [0001] The present invention relates to the field of timing control, and more particularly to a timing signal generating method and apparatus for high stability. Background technique [0002] In the experimental device of nuclear magnetic resonance, quantum calculation, ultrasonic, medical test, any timing signal generator (ATG) has an important role in coordination and synchronization control of the various parts of the device system. By generating a timing trigger pulse different from the delay, the device can accurately control each module in the system, the startup time of each action, coordinates the operation of each component in the system, thereby triggering or external signal triggering inside instructions In the case, the timing operation is performed correctly according to the set order. [0003] The basic requirement of the timing signal generating device is that the triggering order of each channel pulse is even more programmable control, and the dela...

AI Technical Summary

Problems solved by technology

[0004] At present, the timing signal generator based on FPGA mainly adopts the digital time conversion technology (DTC) based on the carry delay chain. Since the delay value of the delay unit of the carry chain is greatly affected by environmental factors (especially temperature), there is nonlinearity. Larger errors lead to limited accuracy, and additional compensation design and pre-correction are required; in addition, when the general carry chain is used as a DTC for delay or external trigger except for shaking, because its structure has a large spatial span, its output taps to The trace length of a specific final output port is difficult to control to be consistent, causing additional uncontrollable delay differences, and changes with design changes, it is difficult to obtain accurate compensation, resulting in a decrease in delay accuracy; patent CN106656121A discloses a A method that uses a hardware structure (capacitor discharge slope comparison) for delay shake compensation processing is also inaccurate due to the inherent error of the hardware itself and requires an additional compensation structure. The wiring fluctuation of external hardware becomes the source of timing error, and the accuracy of external trigger mode can only reach 0.8ns

These problems lead to the above-mentioned timing signal generation technology having the shortcomings of low delay accuracy, difficult compensation, or insufficient compensation accuracy, and it is difficult to align with the real trigger signal and obtain a timing pulse based on the actual trigger.

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