Convolution acceleration calculation system and method based on in-memory calculation

A computing method and computing system technology, applied in complex mathematical operations, CAD circuit design, special data processing applications, etc., can solve problems such as inability to apply artificial intelligence, low efficiency, and inability to realize large-scale data parallelism, so as to reduce operating efficiency interference, avoiding efficiency loss, and reducing time overhead

Active Publication Date: 2021-03-12
XIAN MICROELECTRONICS TECH INST
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Problems solved by technology

However, in the current SRAM structure in the memory IP calculation, it is necessary to introduce software instructions, which leads t

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  • Convolution acceleration calculation system and method based on in-memory calculation
  • Convolution acceleration calculation system and method based on in-memory calculation
  • Convolution acceleration calculation system and method based on in-memory calculation

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Embodiment Construction

[0035] The present invention is described in further detail below in conjunction with accompanying drawing:

[0036] Such as figure 1 As shown, a convolution acceleration calculation method based on in-memory calculation includes the following steps:

[0037] S1, in the storage mode, load the convolution kernel and the input feature map data into the calculation IP in the memory serially;

[0038] S2. After the data is loaded, in the in-memory calculation IP, the multiplication operation is first performed bit by bit in units of elements, and after the multiplication of an element is completed, the addition operation is performed bit by bit to obtain the partial sum accumulation result;

[0039] S3, when the multiplication and addition operation of an element is over, if a convolution is not over, keep the convolution kernel unchanged, move the element address of the input feature map to the starting address of the next element, and repeat the multiplication and addition operat...

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Abstract

The invention discloses a convolution acceleration calculation system and method based on in-memory calculation, and the method comprises the steps of enabling a convolution kernel and input feature map data to be loaded into an in-memory calculation IP in a storage mode in a serial manner, and enabling a constant parameter convolution kernel in convolution operation and a to-be-processed input feature map to be loaded into a storage device in the storage mode; then switching to an operation mode, completing operand multiplication, partial sum accumulation and operand switching steps by orderly controlling in-memory calculation IP serials, seamlessly connecting all steps of convolution operation according to a period by utilizing a convolution acceleration control structure, and carrying out time sequence scheduling by adopting hardware instead of software, so that the efficiency loss caused by a complex software instruction is avoided, and the efficiency advantage of the in-memory computing IP in the actual large-scale data parallel processing is effectively exerted. According to the invention, the convolution operation is subjected to calculation force acceleration, so that the time overhead of the convolution operation is reduced, and a technical support is provided for the real-time performance of artificial intelligence.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and relates to a convolution acceleration computing system and method based on in-memory computing. Background technique [0002] Currently, one of the keys to improving the performance and efficiency of AI chips lies in the efficient execution of convolution operations. In the traditional Von Neumann architecture, the separation of computing and storage causes the access speed of memory to lag behind the computing speed of the processor, and encounters the so-called memory wall problem. Judging from the current academic research situation, the integrated structure of computing and storage is a better solution. Because the integration of computing and storage does not require a data bus to carry data, it can not only solve the parasitic voltage and parasitic resistance of the data bus. To pass the problem of delay and excess power consumption, but also to solve the problem of mismatch be...

Claims

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Application Information

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IPC IPC(8): G06F30/39G06F17/15
CPCG06F30/39G06F17/15Y02D10/00
Inventor 娄冕谢成民杨靓李立金玉琳朱吉喆
Owner XIAN MICROELECTRONICS TECH INST
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