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Semiconductor storage device

A storage device and semiconductor technology, applied in semiconductor devices, information storage, static memory, etc., can solve the problems of voltage affecting non-selected bit lines or non-selected word lines, misapplication, etc.

Pending Publication Date: 2021-03-12
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] On the other hand, if the transistors of the multiplexer are randomly omitted in order to reduce the layout area, then, for example, the selection voltage may be mistakenly applied to the non-selection bit line or the non-selection word line, or the selection voltage may affect the connection with the selection bit line or selection voltage. Doubts about the voltage of a non-selected bit line adjacent to a word line or a non-selected word line

Method used

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  • Semiconductor storage device
  • Semiconductor storage device
  • Semiconductor storage device

Examples

Experimental program
Comparison scheme
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no. 1 Embodiment approach

[0024] figure 1 It is a block diagram showing a configuration example of the semiconductor memory device according to the first embodiment. The semiconductor storage device 1 can be, for example, a volatile memory such as DRAM (Dynamic Random Access Memory, dynamic random access memory), a NAND (Not And, and non) type EEPROM (Electrically Erasable and Programmable Read-Only-Memory, electrically erasable Programmable read-only memory), ReRAM (Resistive Random Access Memory, resistive random access memory), MRAM (Magnetic Random Access Memory, magnetoresistive random access memory), PCM (Phase Change Memory, phase change memory), etc. volatile memory. In addition, the semiconductor memory device 1 may be, for example, one memory chip, or may be a module such as a DIMM (Dual Inline Memory Module) including a plurality of memory chips.

[0025] figure 1 The illustrated semiconductor memory device 1 is configured as, for example, one memory chip. Hereinafter, the semiconductor ...

no. 2 Embodiment approach

[0060] Figure 5 It is a circuit diagram showing a configuration example of the multiplexer MUX in the column decoder CD of the second embodiment. In the second embodiment, dummy bit lines are provided on both sides of each group GP0, GP1, and each group GP0, GP1 is sandwiched by two dummy bit lines. For example, dummy bit lines BLU10 and BLU11 are provided on both sides of the group GP0, and the group GP0 is sandwiched between the dummy bit lines BLU10 and BLU11. On both sides of the group GP1, there are dummy bit lines BLU12 and BLU13, and the group GP1 is sandwiched between the dummy bit lines BLU12 and BLU13.

[0061] Like the dummy bit lines BLU0 to BLU2 of the first embodiment, the dummy bit lines BLU10 to BLU13 extend along the bit lines BL0 to BL7 to a length equal to or longer than that of the bit lines BL0 to BL7 .

[0062] Transistors Tr10 to Tr13 as second transistors are connected between the dummy bit lines BLU10 to BLU13 and the non-selection signal line VUB. ...

no. 3 Embodiment approach

[0081] Figure 7It is a circuit diagram showing a configuration example of the multiplexer MUX in the column decoder CD of the third embodiment. In the third embodiment, transistors Tr10 to Tr13 as second transistors are respectively connected between the bit lines BL0 , BL3 , BL4 , and BL7 located at both ends of each of the groups GP0 and GP1 and the non-selection signal line VUB. . That is, two transistors are connected to each of the bit lines BL0, BL3, BL4, and BL7 located at both ends of each group GP0, GP1, and one transistor is connected to each of the other middle bit lines BL1, BL2, BL5, and BL6. transistor. Dummy selection signal lines SELU0 , SELU1 as second selection signal lines are provided corresponding to each of the groups GP0 , GP1 . The dummy selection signal line SELU0 is commonly connected to the gate electrodes of the transistors Tr10 and Tr11 , and the dummy selection signal line SELU1 is commonly connected to the gate electrodes of the transistors T...

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Abstract

Embodiments provide a semiconductor storage device including a multiplexer capable of reducing an arrangement area and suppressing erroneous application of a selection voltage to a non-selection BL ora non-selection WL or variation due to an adjacent selection BL or selection WL. The semiconductor storage device includes first signal lines divided into groups respectively including m (m is an integer equal to or larger than 2) of the first signal lines; and second signal lines. A memory cell array includes memory cells provided to correspond to respective intersections of the first signal lines and the second signal lines. A selection voltage is applied to any of the first signal lines through m global signal lines. First transistors are provided to respectively correspond to the first signal lines and connected between the first signal lines and the global signal lines. First selection signal lines are provided to respectively correspond to the groups and connected to gate electrodesof the first transistors included in a corresponding one of the groups in common. First dummy signal lines are arranged between adjacent ones of the groups, to which a non-selection voltage is applied.

Description

[0001] [Related Application] [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2019-166333 (filing date: September 12, 2019). This application incorporates the entire content of the basic application by referring to this basic application. technical field [0003] This embodiment relates to a semiconductor memory device. Background technique [0004] In recent years, the number of bit lines or word lines has become very large as semiconductor memory devices have increased in capacity. If the number of bit lines or word lines increases, the arrangement area of ​​decoders for selecting bit lines or word lines also increases accordingly. Therefore, it is desired to reduce the arrangement area of ​​a multiplexer for selecting a bit line or a word line in a decoder. [0005] On the other hand, if the transistors of the multiplexer are randomly omitted in order to reduce the layout area, then, for example, the select...

Claims

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Application Information

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IPC IPC(8): G11C7/12G11C7/18G11C8/14G11C8/08
CPCG11C7/12G11C7/18G11C8/14G11C8/08G11C16/08G11C11/4094G11C8/10G11C8/12G11C2207/005G11C2207/002G11C16/26H10B41/27H10B43/27
Inventor 仁木祐介
Owner KIOXIA CORP
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