Trench gate enhanced GaN-based HEMT device and preparation method thereof

An enhanced, trench gate technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as etching damage, and achieve the effect of increasing the threshold voltage and solving the low threshold voltage.

Active Publication Date: 2021-03-16
LATTICE POWER (JIANGXI) CORP
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Problems solved by technology

[0003] In order to overcome the above deficiencies, the present invention provides a trench gate enhanced GaN-based HEMT device and its preparation method, which can effectively solve the problem of etching damage caused by barrier etching in the existing p-type trench gate enhanced HEMT device. question

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  • Trench gate enhanced GaN-based HEMT device and preparation method thereof

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Embodiment Construction

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative efforts, and obtain other implementations.

[0019] like figure 1 Shown is a schematic structural diagram of the trench gate enhanced GaN-based HEMT device provided by the present invention. It can be seen from the figure that the HEMT device sequentially includes a substrate layer, a buffer layer, a first withstand voltage layer, and a strip mask from bottom to top. layer, the second withstand voltage layer, the channel layer, the barrier layer, the PGaN layer, the source electrode, the drain electrode an...

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Abstract

The invention provides a trench gate enhanced GaN-based HEMT device and a preparation method thereof. The HEMT device sequentially comprises a substrate layer, a buffer layer, a first pressure-resistant layer, a strip-shaped mask layer, a second pressure-resistant layer, a channel layer, a barrier layer, a PGaN layer, a source electrode, a drain electrode and a grid electrode from bottom to top, wherein the strip-shaped mask layer is located in a preset area of the surface of the first pressure-resistant layer, the upper surface of the channel layer is provided with a V-shaped groove, and theV-shaped groove is located above the strip-shaped mask layer; the thickness of the barrier layer in the V-shaped groove is 1/2-1/5 of the thickness of the horizontal surface of the channel layer; thePGaN layer is located on the surface of the V-shaped groove, the grid electrode is located on the surface of the PGaN layer, and the source electrode and the drain electrode are located on the surfaceof the channel layer. The problem of etching damage caused by barrier etching in an existing p-type trench gate enhanced HEMT device is effectively solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a trench gate enhancement type GaN-based HEMT device and a preparation method thereof. Background technique [0002] Compared with depletion-mode GaN-based HEMTs, enhancement-mode HEMTs have important advantages of failsafe and simple driving. The method for realizing the enhancement mode HEMT device includes trench gate, p-type gate, fluorine ion implantation under the gate, and cascade structure cascode. Considering the consistency and repeatability of the production process, the current enhanced HEMTs that can be introduced into production are p-type trench gate and cascode structures. However, these two structures still have their own shortcomings. Among them, the cascode structure cascades a depletion-mode HEMT and a low-voltage MOSFET. Due to the introduction of additional power dissipation and the existence of cascaded parasitic inductance, the cascode structure HE...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/778H01L29/423H01L29/06H01L21/335
CPCH01L29/7783H01L29/7786H01L29/4236H01L29/0603H01L29/0684H01L29/66462
Inventor 付羿周名兵
Owner LATTICE POWER (JIANGXI) CORP
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