Check patentability & draft patents in minutes with Patsnap Eureka AI!

Method for ensuring data crash consistency in secure nonvolatile memory and processor

A non-volatile and consistent technology, applied in electrical digital data processing, memory systems, memory address/allocation/relocation, etc., can solve problems such as high transaction execution delay and write amplification cannot be effectively balanced, to avoid persistence Order constraints, reduce waiting delay, and improve the effect of scalability

Active Publication Date: 2021-03-23
HUAZHONG UNIV OF SCI & TECH
View PDF0 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides a method and a processor for ensuring data crash consistency in a secure non-volatile memory, which are used to solve the problem of high transaction execution delay and write amplification when balancing the security of non-volatile memory and data crash consistency. Phenomena that lead to technical problems that cannot be effectively balanced

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for ensuring data crash consistency in secure nonvolatile memory and processor
  • Method for ensuring data crash consistency in secure nonvolatile memory and processor
  • Method for ensuring data crash consistency in secure nonvolatile memory and processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] A method for guaranteeing data crash consistency in secure non-volatile memory, such as figure 1 As shown, including: adding a transaction persistence sequence control engine in the processor's first-level cache controller; adding three registers in the memory controller to store the ciphertext data, counter blocks, and default The sub-bottom node of the Kerr tree, and the steps for the above processor to process transactions include:

[0040] (1) The transaction persistence sequence control engine controls the refresh and kick-out operations of transaction logs and data in the first-level data cache. The refresh and kick-out operations of transaction log cache lines are immediately persisted (that is, written) to memory In this way, the refresh operation of the transaction data cache line adopts the method of first persisting the corresponding log cache line in the first-level data cache and then persisting the data cache line;

[0041] The method of this embodiment a...

Embodiment 2

[0055] A processor that guarantees data crash consistency in a secure non-volatile memory, including: a processor core, a first-level data cache, a first-level cache controller, and a memory controller, wherein the first-level cache controller includes a transaction persistence sequence Control engine; the memory controller includes three registers for storing the ciphertext data, the counter block, and the sub-bottom node of the Merkle tree that need to be persisted to the memory together; among them,

[0056] The transaction persistence sequence control engine is used to control the refresh and kick operations of transaction logs and data in the first-level data cache. Among them, the refresh and kick operations of transaction log cache lines are immediately written into memory, and the transaction data cache The line refresh operation takes the method of first writing the corresponding log cache line in the first-level data cache into the memory, and then writing the data ca...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention belongs to the field of computer data storage, and particularly relates to a method and a processor for ensuring data crash consistency in a safe nonvolatile memory, which comprises thefollowing steps of: adding a transaction persistence sequence control engine in a primary cache controller for controlling a persistence sequence of logs and data in transactions, wherein the engine adopts a mode of immediate persistence to a memory for refreshing and kicking-out operations of a log cache line, and adopts a mode of persisting the corresponding log cache line in a cache and then persisting the data cache line for refreshing operations of a data cache line; a memory controller receives a write request from a cache, persists data, a counter block and a Merkel tree sub-bottom layer node in advance without waiting for a Merkel tree to be completely updated, writes a secondary counter and a log entry into a memory in parallel, and merges write-in of security metadata in a writequeue according to address information. According to the method, the balance of the nonvolatile memory system between the security and the crash consistency is ensured, the transaction execution delayis reduced, and the write life of the system is prolonged.

Description

technical field [0001] The invention belongs to the field of computer data storage, and more specifically relates to a method and a processor for ensuring data crash consistency in a safe non-volatile memory. Background technique [0002] The traditional memory technology DRAM is limited by the manufacturing process and refresh power consumption, and it is difficult to provide a larger capacity to meet the memory requirements of computer systems in the era of big data. New non-volatile memory technologies (NVM), such as phase-change memory (PCM), resistive-change memory (ReRAM) and self-transfer torque random access memory (STT-RAM), are non-volatile and have similar performance to DRAM. With high storage density and low energy consumption, it is expected to become the next generation memory technology. And with the release of Intel Optane DCPersistent Memory, non-volatile memory technology will be widely deployed. [0003] Due to non-volatility, there are two challenges i...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F12/02G06F12/0811G06F11/34
CPCG06F12/0238G06F12/0811G06F11/3476
Inventor 华宇李璇徐豪陈章玉
Owner HUAZHONG UNIV OF SCI & TECH
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com