Verilog file conversion method and device, storage medium and equipment

Abstract

One or more embodiments of the present invention disclose a Verilog file conversion method and device, a storage medium and equipment; the method comprising: obtaining an original Verilog file and a configuration file, the configuration file comprising information of a target expression mode corresponding to a target electronic design automation (EDA) tool; obtaining a target code for describing alogic function from the original Verilog file; converting the target code into a file expressed in the target expression mode to obtain a converted file; generating a first test excitation file according to the target code; according to the first test excitation file, carrying out simulation test on the original Verilog file and the converted file to obtain a first test result; and judging whether the functions of the converted file are consistent with those of the original Verilog file or not according to the first test result. By means of the method, the universality of the Verilog file canbe improved.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a Verilog file conversion method, device, storage medium and equipment. Background technique [0002] At present, in integrated circuit design, it can be mainly divided into semi-custom circuit design process and full-custom circuit design process. Among them, semi-custom circuit design refers to the behavior-level description of the chip using a hardware description language (Verilog or VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language, very high-speed integrated circuit hardware description language)) according to the chip design specification, Among them, Verilog is Verilog HDL, which is a hardware description language that describes the structure and behavior of digital system hardware in text form. Then use a synthesis tool to convert the hardware description language into a gate-level netlist, and finally use an automatic layout and routing tool to...

AI Technical Summary

Problems solved by technology

In this way, the Verilog of the fully customized circuit design module is often incompatible with the EDA tools of the subsequent process.

It may even occur that the Verilog file in the semi-custom design process may be compatible with some EDA tools in the subsequent process, but not compatible with other EDA tools, resulting in poor portability of the Verilog file

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