Command scheduling method, device and equipment and storage medium

Abstract

The invention provides a command scheduling method, device and equipment, and a storage medium. The method comprises the steps of obtaining refreshing times of a storage array; when the refreshing frequency reaches a first preset frequency, generating a temperature state reading request of the storage array, and executing the temperature state reading request; obtaining the current temperature state reading frequency of the storage array; judging whether the temperature state reading frequency reaches a second preset frequency or not; if the temperature state reading frequency reaches the second preset frequency, generating a drift compensation operation request of a data gating signal of the storage array; and in an exclusive arbitration time interval, continuously executing the temperature state reading request or the temperature state reading request and the drift compensation operation request on all the storage arrays, and resetting the temperature state reading times. According to the invention, the number of bit widths of the counter is reduced, hardware resources are saved, and the complexity of the arbiter is reduced.

Description

technical field [0001] The present application relates to the technical field of memory, and in particular, to a command scheduling method, device, device and storage medium. Background technique [0002] DDR5 SDRAM is the fifth-generation double data rate synchronous dynamic random memory chip particle. Compared with DDR4, its IO interface voltage is reduced, the interface rate is greatly improved, the memory capacity is larger, and the interface signal is reduced, so it can provide low power consumption and high bandwidth, high-capacity memory system. From the perspective of reducing power consumption, DDR5 particles adopt the unbalanced design of the data strobe signal DQS on the data bus and the DQ delay of the data line, and reduce the number of DQ data line buffer gates to achieve the purpose of reducing power consumption. In the new design, since DQS and DQ have different numbers of delay cells in DRAM (Dynamic Random Access Memory, dynamic random access memory), the...

AI Technical Summary

Problems solved by technology

[0007] If the DDC and TCR control logic make separate requests according to each Rank and are arbitrated by the arbitrator, the intervals between the requests made by the DDC and TCR control logic are different, and there are separate counters for timing, which makes the controller clock count bit width too large, and Use multiple counters, resulting in waste of resources

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