Preparation method of integrated circuit
An integrated circuit and electrode layer technology, which is applied in the field of semiconductor integrated circuit preparation, can solve problems such as waste of cost and resources, and achieve the effect of reducing costs
Active Publication Date: 2021-04-06
NEXCHIP SEMICON CO LTD
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[0003]The object of the present invention is to provide a method for preparing an integrated circuit, which solves the problem that a photomask needs to be designed for each alignment layer in the semiconductor manufacturing process, resulting in waste of cost and resources The problem
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[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0039] Photolithography technology is the basis of large-scale integrated circuit manufacturing technology, which largely determines the integration level of integrated circuits. The so-called photolithography is to transfer the pattern on the mask plate, that is, the photomask, to the wafer coated with photoresist through exposure, and the pattern on the photomask appears on the wafer after development. In the manufacturing process of integrated circuits, it is us...
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Abstract
The invention discloses a preparation method of an integrated circuit, which at least comprises the following steps of: providing a photomask, and arranging a plurality of first alignment marks and a plurality of second alignment marks at the edge area of the photomask; forming a plurality of first alignment mark patterns and a plurality of second alignment mark patterns in the cutting channel area of the wafer substrate through a photomask; aligning the photomask with the machine table by using a plurality of first alignment marks; forming a plurality of thin film layers on the wafer substrate; arranging a photomask on the plurality of thin film layers, and forming a plurality of first alignment mark patterns and a plurality of second alignment mark patterns in the cutting channel area of the wafer substrate through the photomask; forming a first electrode layer on the plurality of thin film layers, wherein the first electrode layer is aligned through a plurality of second alignment marks; and forming a second electrode layer on the first electrode layer, wherein the second electrode layer is aligned through a plurality of second alignment marks. According to the invention, the problem of cost and resource waste caused by the fact that each alignment layer needs to be provided with a photomask in the semiconductor manufacturing process can be improved.
Description
technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, in particular to a method for preparing a semiconductor integrated circuit. Background technique [0002] The interface between IC design and semiconductor process fabrication is layout. The layout of an integrated circuit is a combination of geometric figures corresponding to the structure of circuit components on a wafer, but these geometric figures are composed of graphics of different layers. The integrated circuit manufacturer transfers the pattern of the layout designed by the design engineer to the wafer, and needs to make a set of corresponding photolithography mask, that is, a photomask. The purpose of plate making is to produce a set of layered layout photolithography masks for future pattern transfer (lithography and etching). In order to ensure the quality of integrated circuits, it is necessary to ensure the accuracy of overlay alignment between different ...
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IPC IPC(8): H01L21/68H01L23/544G03F9/00
CPCH01L21/682H01L23/544G03F9/7073H01L2223/54426
Inventor 魏姣阳杜雷张永忠叶伟余仁
Owner NEXCHIP SEMICON CO LTD