Semiconductor device, method for manufacturing semiconductor device, and mask plate system

Abstract

The invention provides a semiconductor device, a method for manufacturing the semiconductor device, and a mask plate system. The semiconductor device comprises: a substrate; a stacking structure, which is arranged on the substrate; a conductive channel layer, which is arranged on the stacked structure and comprises a plurality of conductive channels; a redistribution layer, which is arranged on the conductive channel layer and comprises a plurality of redistribution conductive parts in one-to-one correspondence with the conductive channels; an interconnection layer, which is located on the redistribution layer, wherein each redistribution conductive part comprises a first end face and a second end face which are oppositely arranged in the stacking direction of the stacking structure, the conductive channels are electrically connected with the redistribution conductive parts at the first end faces, the redistribution conductive parts extend in a direction perpendicular to the stacking direction, the second end faces comprise in-situ connection areas deviating relative to the conductive channels, and the interconnection layer is electrically connected with the redistribution conductive parts in the in-situ connection areas.

Description

technical field [0001] The present application relates to the semiconductor field, and more specifically, to a semiconductor device, a method for manufacturing the semiconductor device, and a mask system. Background technique [0002] In the information age, data storage is very important. Various types of memories are continuously being designed. For example, people seek to increase the storage density of memory, and thus three-dimensional NAND flash (3D NAND flash) has been more and more widely used. [0003] When manufacturing 3D NAND flash memory, stacking structures are usually included. Steps are etched out of the stack structure, and then the stack structure includes a core area (GB Area) and a step area (SS Area). [0004] For a stacked structure with a large number of stacks, two etchings are required to manufacture the lower channel hole and the upper channel hole in the core area of ​​the stacked structure, and the upper channel hole needs to be overlaid with t...

AI Technical Summary

Problems solved by technology

[0006] Data collection for new flash memory structures and validation of new reticles typically takes up to three to four months, which greatly hinders rapid development of R&D

In addition, because every time a new process is added to the production, this process must be carried out again, so it brings great uncertainty to the future progress of the ongoing project, making the risk of the project greater

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