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Chip substrate and mainboard

A substrate and chip technology, applied in printed circuit components, circuit electrostatic discharge protection, overvoltage protection, etc., can solve problems such as occupying motherboard space, unfavorable development trend of product miniaturization and integration, and adverse effects of high-speed signal transmission , to achieve the effect of improving anti-static ability and improving space utilization

Pending Publication Date: 2021-04-06
HYGON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] (1) A separate TVS (Transient Voltage Suppressor, transient diode) device will occupy a part of the motherboard space, which is not conducive to the development trend of product miniaturization and integration;
[0005] (2) Separately encapsulating TVS on the surface of the motherboard will bring certain parasitic parameters, which will have a negative impact on high-speed signal transmission

Method used

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  • Chip substrate and mainboard
  • Chip substrate and mainboard
  • Chip substrate and mainboard

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] This embodiment provides a chip substrate, combined with figure 1 , the chip substrate includes: a substrate body 2 , a chip body 1 and an electrostatic protection device 3 .

[0037] Both the chip body 1 and the electrostatic protection device 3 are fixedly connected to the substrate body 2; the substrate body 2 is provided with a signal wiring group, and the chip body 1 is electrically connected to the signal wiring group; The electrostatic protection device 3 is electrically connected to the signal wiring group.

[0038] Wherein, the electrostatic protection device 3 includes: a transient diode and / or an electrostatic discharge diode. The electrostatic protection device 3 includes: a ground pin and a first signal pin. The first signal pin is electrically connected to the signal wiring group, and the ground pin is electrically connected to the ground layer 74 in the substrate body 2 .

[0039] Further, the substrate body 2 includes: a first surface 21 and a second ...

Embodiment 2

[0046] On the basis of Example 1, combined with figure 2 with Figure 4 , this embodiment provides a chip substrate, including: the substrate body 2 and the electrostatic protection device. Wherein, the electrostatic protection device 3 includes: a TVS and / or an electrostatic discharge diode. In this embodiment, the electrostatic protection device is a TVS. The TVS is provided with two Pins, which are IO Pin71 and GND Pin, namely the first signal pin and a ground pin; the IO Pin71 is used for connecting signals, and the GND Pin is used for connecting GND.

[0047] Further, the substrate body 2 has 4 pairs of signal lines 75, which are respectively 3 pairs of data lines D2+ / D2-, D1+ / D1-, D0+ / D0- and a pair of clock lines Clk+ / Clk-; the substrate body 2 There are also five sets of ground planes 74 , namely GND. Five sets of ground layers 74 are interspersed with four pairs of signal lines 75 , and two ends of each set of ground layers 74 are respectively provided with GND v...

Embodiment 3

[0049] Based on the chip substrate provided in the second embodiment, in this embodiment, the signal line 75 is routed to the inner layer, and connected to the pad and the wiring of the electrostatic protection device 3 through the substrate via hole 24 .

[0050] Specifically, combine Figure 5, the PCB trace 25 is in the inner layer of the substrate body 2, the TVS is on the TOP surface, and the PCB trace 25 is connected to the IO Pin71 of the TVS through the substrate via hole 24, and the GND pin73 of the TVS is connected to the IO Pin71 of the TVS through the copper laying and the via hole. The inner layer GND of the substrate body 2 is connected.

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Abstract

The invention provides a chip substrate and a mainboard. The chip substrate comprises a substrate body, a chip body and an electrostatic protection device, wherein the chip body and the electrostatic protection device are fixedly connected with the substrate body; the substrate body is provided with a signal wiring group, and the chip body is electrically connected with the signal wiring group; and the electrostatic protection device is electrically connected with the signal wiring group. The space utilization rate of the chip substrate can be improved while the anti-static capability of the chip substrate is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a chip substrate and a main board. Background technique [0002] The main culprit of EOS (Electrical Over Stress) damage to all electronic components or integrated circuit systems is electrostatic discharge (ESD, Electrostatic Discharge). [0003] In order to solve the electrostatic discharge problem of electronic components or integrated circuit systems, the existing method is to add TVS diodes on the main board to solve the problem. However, this method is prone to some problems, including: [0004] (1) A separate TVS (Transient Voltage Suppressor, transient diode) device will occupy a part of the motherboard space, which is not conducive to the development trend of product miniaturization and integration; [0005] (2) Separately encapsulating the TVS on the surface of the motherboard will bring certain parasitic parameters, which will adversely affect high-speed ...

Claims

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Application Information

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IPC IPC(8): H05K1/02
CPCH05K1/0259H05K1/0296
Inventor 逯永广杨晓君杜树安钱晓峰杨光林
Owner HYGON INFORMATION TECH CO LTD