652results about "Circuit electrostatic discharge protection" patented technology

An LED apparatus includes a base having thermal conductivity, an insulative substrate provided on one surface of the base and including electrodes provided on a surface of the substrate, at least one base-mounting area that is an exposed part of the base, exposed within a pass-through hole provided in the substrate, a plurality of LED elements mounted on the base in the base-mounting area and some of the LED elements in a unit electrically connected to the electrodes in series, a plurality of the units are electrically connected in parallel, and a frame disposed to surround the base-mounting area and configured to form a light-emitting area.

There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and / or utilize the side surface of an assembled flexible display.

A filter for use in a coaxial cable network includes a printed circuit board having first and second opposed major surfaces, and first and second opposing sides. The opposed major surfaces are substantially parallel to a single plane, and are bisected by a longitudinal axis. The first and second opposing sides are substantially parallel to the longitudinal axis. The filter further includes an input terminal and an output terminal connected to the printed circuit board. The input terminal and the output terminal have an axis extending substantially parallel to the longitudinal axis. A signal path is disposed on the printed circuit board and extends from the input terminal toward the output terminal. The filter further includes a plurality of resonator elements fabricated upon the first opposed major surface. In one embodiment, the inductor elements are arranged in series along the signal path defining a footprint of less than 540 square millimeters. The filter passes a first range of frequencies in a provider bandwidth and attenuates a second range of frequencies in a personal data network bandwidth. In one embodiment, the resonator elements are parallel inductor elements and capacitor elements, the inductor elements being etched spiral inductors.

Nanotube ESD protective devices and corresponding nonvolatile and volatile nanotube switches. An electrostatic discharge (ESD) protection circuit for protecting a protected circuit is coupled to an input pad. The ESD circuit includes a nanotube switch electrically having a control. The switch is coupled to the protected circuit and to a discharge path. The nanotube switch is controllable, in response to electrical stimulation of the control, between a de-activated state and an activated state. The activated state creates a current path so that a signal on the input pad flows to the discharge path to cause the signal at the input pad to remain within a predefined operable range for the protected circuit. The nanotube switch, the input pad, and the protected circuit may be on a semiconductor chip. The nanotube switch may be on a chip carrier. The deactivated and activated states may be volatile or non-volatile depending on the embodiment. The ESD circuit may be repeatedly programmed between the activated and deactivated states so as to repeatedly activate and deactivate ESD protection of the protected circuit. The nanotube switch provides protection based on the magnitude of the signal on the input pad.

A voltage variable material (“VVM”) including an insulative binder that is formulated to intrinsically adhere to conductive and non-conductive surfaces is provided. The binder and thus the VVM is self-curable and applicable in a spreadable form that dries before use. The binder eliminates the need to place the VVM in a separate device or to provide separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid FR-4 laminate, a polyimide, a polymer or a multilayer PCB via a process such as screen or stencil printing. In one embodiment, the VVM includes two types of conductive particles, one with a core and one without a core. The VVM can also have core-shell type semiconductive particles.

A flexible printed circuit board (FPCB) and FPCB manufacturing method that improves a signal transfer characteristic at a high speed. The FPCB includes an insulating layer having a signal pattern that transfers signals, a cover layer formed on the signal pattern, and a shielding layer formed at a position opposite to the signal pattern. The shielding layer faces at least one of the insulating layer and the cover layer across anspace formed there between.

Techniques for preventing electrostatic discharge (ESD) and circuit noise are provided. More particularly, the present invention provides a method to prevent ESD damage during the assembly of computer disk commonly called a hard disk for memory applications. The coating mainly involves a ion-deposition process. Merely by way of example, the present invention is implemented by using filtered cathodic vacuum arc (FCVA) with a dissipative crystalline and / or amorphous carbon base thin film coating on a flexible circuit to drain the potential electrostatic charges during circuit assembly and interconnect processes, yet it would be recognized that the invention has a much broader range of applicability on any electronic apparatus that is susceptible to electrostatic damage and static noise.

The present invention provides overvoltage circuit protection. Specifically, the present invention provides a voltage variable material (“VVM”) that includes an insulative binder that is formulated to intrinsically adhere to conductive and nonconductive surfaces. The binder and thus the VVM is self-curable and may be applied to an application in the form of an ink, which dries in a final form for use. The binder eliminates the need to place the VVM in a separate device or for separate printed circuit board pads on which to electrically connect the VVM. The binder and thus the VVM can be directly applied to many different types of substrates, such as a rigid (FR-4) laminate, a polyimide or a polymer. The VVM can also be directly applied to different types of substrates that are placed inside a device.

Devices capable of protecting electronic components during the occurrence of a disturbance event using printed circuit board manufacturing techniques. A three (3) layer structure is formed comprising a polymer-based formulation sandwiched between two electrode layers. The devices can be manufactured in panel form providing high quantities of devices which can be removed from the panel and applied directly to the component to be protected. Desired patterns can be formed on either one of the electrode layers by photo-etch techniques thereby providing a process that can be tailored to a large number of applications.

An improved electrical circuit that includes an embedded electrical component and an embedded voltage variable material (“VVM”) is provided. In one embodiment, the embedded VVM is provided as a voltage variable substrate, which is used in combination with an embedded electrical component, such as an embedded resistive material or an embedded capacitive material.

A system and method for implementing an electronic circuit for protecting electronic components from ESD. A PCB or IC may include an electrostatic discharge protection layer having a first and second conductive layer separated by a semi-conductive dielectric layer. Further, the PCB / IC may include a protected node coupled to the first conductive layer and a current-shunt node electrically coupled to the second conductive layer, such that a signal at the protected node that is below a threshold magnitude propagates through the protected node in a normal operating path and a signal at the protected node that exceeds a threshold magnitude is diverted to the semi-conductive dielectric layer to the current-shunt node in a current-shunt path. In this manner, existing layers of a PCB / IC may be used for both ESD protection and other functions, such as ground planes or battery plane by isolating the specific sections of the layer for its intended use.

A wired circuit board has a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer and including at least one pair of wires arranged in mutually spaced-apart and opposed relation having different potentials, a semiconductive layer formed on the insulating base layer to cover the conductive pattern and electrically connected to the metal supporting board on one side outside a region where the pair of wires are opposed, and an insulating cover layer formed on the semiconductive layer.

A touch panel includes a substrate, a plurality of first axis electrodes, a plurality of second axis electrodes and a first insulation layer. Each first axis electrode includes a plurality of first sub-electrodes and a plurality of first connection parts disposed between two adjacent first sub-electrodes. The first sub-electrodes and the first connection parts are monolithically formed. Each second axis electrode includes a plurality of second sub-electrodes and a plurality of second connection parts disposed between two adjacent second sub-electrodes. The second sub-electrodes and the second connection parts are monolithically formed. The first sub-electrodes and the second sub-electrodes are disposed on an identical surface. The first insulation layer is disposed on and completely covers the first axis electrodes. The first insulation layer is partially disposed between the first connection part and the second connection part. The first axis electrodes are disposed between the first insulation layer and the substrate.

A shield layer is selectively formed on a front surface of a base film having an insulating property to form a wiring layer on a rear surface of the base film, and a connector connection terminal and a mounting terminal are selectively provided on the wiring layer. A liquid crystal display device is configured so as to be housed in a set housing, in a state that a TFT array substrate and a control board are connected to each other via an FPC having the structure as described above. In this case, the shield layer is provided in such a manner of opposing to an inner surface of the housing, the shield layer maintains an insulating relationship with the drive circuit, and is electrically connected to a portion of the housing via the first ground wiring portion.

Provided is a display device including: a display panel; a chip on film (COF) coupled to the display panel; a flexible printed circuit board (FPCB) coupled to the chip on film, the flexible printed circuit board including a plurality of conductive layers and a plurality of insulating layers, the insulating layers being interposed between the conductive layers or being located at opposite sides of the flexible printed circuit board; and a protecting sheet at one side of the display panel and including a conductive region. One of the insulating layers at one side of the flexible printed circuit board is an opening region of the one of the insulating layers and exposes a corresponding one of the conductive layers to at least partially contact the conductive region.

The present invention relates to electrically conductive polyimide films having dispersed in them electrically conductive polymer particles having an average particle size from 0.5 to 5.0 microns. These films are suitable as image transfer belts in high-speed color copying machines and possess a surface smoothness, Ra factor (microns), between 0.5 and 1.5 and a gloss factor between 70 and 120.

A circuit board for semiconductor package is designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges. The printed circuit board for semiconductor package includes: a resinous substrate; a chip mounting region formed on the top surface of the resinous substrate for mounting a semiconductor chip thereon; a plurality of fine circuit patterns radially disposed in the circumference of the chip mounting region and extending to the edge of the chip mounting region; a plurality of ball lands formed in an array on the bottom surface of the resinous substrate, to be fused to conductive balls; a conductive via hole connecting the circuit patterns on the top surface of the resinous substrate to the ball lands on the bottom surface of the resinous substrate; a cover coat applied to the top and bottom surfaces of the resinous substrate to protect the circuit patterns from an external environment and make the ball lands open to the exterior; and a means for removing electrostatic charges provided at the edge of the substrate and connected to the plural circuit patterns to remove electrostatic charges in the manufacture of semiconductors.

A head suspension prevents a read element from electrostatic discharge damage without employing a static electricity remover, and at the same time, secures the frequency characteristics of a write signal. The head suspension has a load beam to apply load to a slider that writes and reads data to and from a hard disk, a flexture made of a conductive thin plate attached to the load beam, to support the slider, write wires connected to the slider and formed on an insulating base layer that is made of flexible resin and is formed on the flexure, and coating made of conductive flexible resin to discharge static electricity. The coating is formed over the read wires and is extended to the surface of the flexure.

A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

A display device having a display panel, a conductive shielding film disposed on a surface of the display panel, and a flexible circuit unit connected to another surface of the display panel and configured to provide a driving signal to the display panel, wherein the shielding film has at least one protrusion disposed adjacent the flexible circuit unit.

A head suspension prevents a read element from electrostatic discharge damage without employing a static electricity remover or without increasing the number of manufacturing processes. The head suspension has a load beam to apply load to a head (21) that writes and reads data to and from a hard disk, a flexure (7) made of a conductive thin substrate attached to the load beam and supporting the head, an insulating base layer (35) made of flexible resin and formed on the substrate of the flexure, write wires (29) and read wires (31) connected to the head and formed on the insulating base layer, and an insulating cover layer (41, 43) covering the write and read wires on the insulating base layer. The insulating cover layer (41, 43) is made of slightly conductive flexible resin.

A peripheral circuit structure disposed on a substrate having an element region and a peripheral circuit region is provided. The peripheral circuit structure located in the peripheral circuit region includes first pads, second pads, a first trace, a second trace and third traces connected to the second pads and a device located in the element region. The first pads include a first ground pad and a second ground pad. The second pads are located between the first ground pad and the second ground pad. Two ends of the first trace are respectively electrically connected to the first ground pad and the second ground pad. Two ends of the second trace are respectively electrically connected to the first ground pad and the second ground pad, so that the second trace, the first trace, the first ground pad and the second ground form a closed loop.