Novel parallel-serial conversion circuit

Abstract

The invention relates to a novel parallel-serial conversion circuit, which belongs to the technical field of high-speed serial interfaces and comprises a data preprocessing circuit, a data synthesis circuit and a driver circuit. The data preprocessing circuit sends preprocessed N bits of data Qn<1> , Qn<2> ,..., Qn<N-1>, Qn<N> to the data synthesis circuit, and carries out exclusive-OR logic and XNOR logic operations by use of reverse data QnN<N> of the N-th bit of preprocessed data with the input N bits of parallel data Sn<1> , Sn<2> ,..., Sn<N-1> , Sn<N>. According to the invention, a traditional parallel-serial conversion mode is replaced by the data preprocessing circuit and the driver circuit, and the problems of channel charge injection, clock feedthrough and multi-phase clock in parallel-serial conversion are solved.

Description

technical field [0001] The invention relates to a novel parallel-to-serial conversion circuit, belonging to the technical field of high-speed serial interfaces. Background technique [0002] In recent years, the rapid development of the integrated circuit industry and the increasing progress of information technology have made people's demand for data processing more and more, and the electronic devices as information carriers work faster and faster. The main frequency of the chip has reached several GHz or even more than ten GHz, but the data transmission rate between the chips is much lower, so the data transmission rate between the chips has become the main factor restricting the performance of the chip. High-speed serial transmission technology (SerDes) can reduce the number of required channels and device pins, reduce communication costs, and increase signal transmission speed. Therefore, it is very important to improve the transmission rate of the high-speed serial in...

AI Technical Summary

Problems solved by technology

[0003] In the traditional parallel-to-serial conversion method, the tree-structured parallel-to-serial conversion method will be affected by channel charge injection and clock feedthrough effects, which will affect the accuracy of data transmission and lead to an increase in the bit error rate; the parallel structure The parallel-to-serial conversion method needs to provide a large number of multi-phase clocks; the shift register type parallel-to-serial conversion method will face the challenges of high clock rate requirements, power consumption and large area

At the same time, these structures require drivers with high input bandwidth to send data

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