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Dielectric temperature coefficient corrected deep energy level transient spectrum testing method

A technology of temperature coefficient and test method, applied in the direction of semiconductor/solid-state device test/measurement, circuit, electrical components, etc., can solve inaccurate problems

Active Publication Date: 2021-05-11
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Problems solved by technology

[0005] In view of the above-mentioned problems or deficiencies, the purpose of the present invention is to provide a dielectric temperature coefficient correction method for MIS structure devices whose dielectric constant is dependent on temperature Deep-level transient spectrum test method to improve the applicability of DLTS technology and solve the inaccurate problem of current DLTS technology in this situation

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  • Dielectric temperature coefficient corrected deep energy level transient spectrum testing method
  • Dielectric temperature coefficient corrected deep energy level transient spectrum testing method
  • Dielectric temperature coefficient corrected deep energy level transient spectrum testing method

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specific Embodiment approach

[0035] Specific embodiments: a method for testing deep-level transient spectrum with dielectric temperature coefficient correction. In this embodiment, the target sample is a MOS device with a metal-oxide layer-semiconductor layer structure.

[0036] Step 1: carry out C-V test to target sample (such as figure 2 ) and determine that the sample bias voltage is -5V, the pulse height is 3V and the pulse width is 10ms. Ensure that the test parameters are within the range of the test system. The samples were tested by DLTS, and the capacitance transient information of the samples at different temperatures was collected for analysis. Get the capacitance transient C-t curve at different temperatures, and then select two fixed times t 1 , t 2 (Such as image 3 ) and its corresponding capacitance change can be expressed as:

[0037]

[0038] where C(t 1 ), C(t 2 ) is t1 , t 2 Test capacitance at moment, n T is the electron concentration in the trap, C 0 is the defect capac...

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Abstract

The invention belongs to the technical field of testing of semiconductor devices, and particularly relates to a dielectric temperature coefficient corrected deep energy level transient spectrum testing method. According to the method, the equivalent circuit of the DLTS test is combined, the influence of the insulation layer capacitance in the MIS structure on the DLTS signal is analyzed, then the DLTS test data is analyzed, the influence factor alpha of the insulation layer capacitance in the MIS structure is calculated, then the original DLTS signal spectrum is corrected according to the DLTS spectral line data and the influence factor, and the accurate DLTS signal spectrum is obtained. According to the invention, the problem that the existing DLTS test is inaccurate when the MIS structure is made of a material with dielectric constant dependent on temperature is solved, and finally, the defect level, the sinking concentration and the interception area of the MIS structure are accurately obtained.

Description

technical field [0001] The invention belongs to the technical field of testing semiconductor devices, and relates to a method for measuring DLTS based on lock-in amplification technology, more specifically a method for testing deep-level transient spectrum with dielectric temperature coefficient correction. Background technique [0002] Deep level transient spectroscopy (DLTS) is an important technical means in the semiconductor field to study and detect semiconductor impurities, defect deep levels and interface states. When applied to the field of semiconductors, it can give the DLTS spectrum that characterizes the distribution of impurities, defect deep energy levels, and interface states with temperature (ie energy) within the semiconductor band gap; DLTS can explain the degradation of the electrical characteristics of semiconductor devices with changes in microscopic physical quantities reason. [0003] DLTS technology was first applied to samples with asymmetric PN jun...

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Application Information

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IPC IPC(8): H01L21/66
CPCH01L22/12H01L22/14
Inventor 曾慧中唐义强孟奔阳肖化宇杨潇张文旭张万里李言荣
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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