Communication method and communication system of interconnected die and DSP/FPGA

Abstract

The invention relates to a communication method and a communication system of an interconnected die and a DSP / FPGA. According to the communication method of the interconnection die and the DSP / FPGA, a plurality of data interfaces are included, each data interface is provided with a different protocol conversion module, and data input conversion and data output conversion are included during communication of the data interfaces; during data input conversion, external data of the DSP / FPGA is converted into a unified data protocol format through a protocol conversion module and is transmitted to a die level network in the interconnected die for unified transmission of the data; during data output conversion, the internal data in the interconnection die is converted into different data protocol formats by the protocol conversion module according to the data property of the data, enters different data interfaces and is transmitted to the DSP / FPGA. According to the method, the external data and the internal data are mutually converted, so that each apparatus and device can be connected into the multi-die system in any form, the flexibility of the system is improved, and flexible assembly, rapid definition and rapid implementation of the system are facilitated.

Description

technical field

[0001] The invention relates to a communication system with DSP / FPGA, in particular to a communication method and communication system between interconnected bare cores and DSP / FPGA. Background technique

[0002] With the development of digital integrated circuits, system on chip (System on Chip, SoC, refers to the integration of multiple functional modules on the same silicon chip) has almost become a necessary solution to realize high-performance systems. Manufacturers continue to expand the SoC Scale to meet the needs of users for product performance. However, limited by processing technology and other factors, Moore's Law (that is, the law that the number of transistors that can be accommodated on an integrated circuit doubles every 24 months) is gradually failing, which makes it impossible to expand the scale of integrated circuits on a single silicon chip. Costs and development cycles become extremely high.

[0003] In the future, integrated circuits ...

Examples

Embodiment 1

[0019] Such as figure 1 and figure 2 As shown, the communication method between the interconnected bare core and DSP / FPGA includes a plurality of data interfaces, each of which is provided with a different protocol conversion module, and the data interface includes data input conversion and data output conversion during communication; When the data input is converted, the external data of the DSP / FPGA is converted into a unified data protocol format by the protocol conversion module and transmitted to the bare core level network inside the interconnected bare core for unified data transmission; when the data output is converted, the interconnected bare core The internal data inside the core is converted into different data protocol formats by the protocol conversion module according to the data nature of the data itself, and enters different data interfaces for transmission to DSP / FPGA.

[0020] Such as figure 1 As shown, the interior of the interconnected bare core is an i...

Embodiment 2

[0023] Such as figure 1 and figure 2 As shown in the communication system of the interconnected bare core and DSP / FPGA, the interconnected bare core is provided with a plurality of data interfaces, and a plurality of the data interfaces are used to connect with the DSP / FPGA, and each of the data interfaces is provided with a different A protocol conversion circuit, the protocol conversion circuit is used to convert different external data into a unified data protocol format into the interconnected bare core and convert the internal data of the interconnected bare core into a corresponding data interface according to the purpose of the data data protocol format.

[0024] The data interface includes a master interface, a slave interface, and a peer interface.

[0025] The master device interface includes: an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, and the interrupt interface is used to receive an interrupt request from the interconnec...

technical field

[0001] The invention relates to a communication system with DSP / FPGA, in particular to a communication method and communication system between interconnected bare cores and DSP / FPGA. Background technique

[0002] With the development of digital integrated circuits, system on chip (System on Chip, SoC, refers to the integration of multiple functional modules on the same silicon chip) has almost become a necessary solution to realize high-performance systems. Manufacturers continue to expand the SoC Scale to meet the needs of users for product performance. However, limited by processing technology and other factors, Moore's Law (that is, the law that the number of transistors that can be accommodated on an integrated circuit doubles every 24 months) is gradually failing, which makes it impossible to expand the scale of integrated circuits on a single silicon chip. Costs and development cycles become extremely high.

[0003] In the future, integrated circuits ...

Examples

Embodiment 1

[0019] Such as figure 1 and figure 2 As shown, the communication method between the interconnected bare core and DSP / FPGA includes a plurality of data interfaces, each of which is provided with a different protocol conversion module, and the data interface includes data input conversion and data output conversion during communication; When the data input is converted, the external data of the DSP / FPGA is converted into a unified data protocol format by the protocol conversion module and transmitted to the bare core level network inside the interconnected bare core for unified data transmission; when the data output is converted, the interconnected bare core The internal data inside the core is converted into different data protocol formats by the protocol conversion module according to the data nature of the data itself, and enters different data interfaces for transmission to DSP / FPGA.

[0020] Such as figure 1 As shown, the interior of the interconnected bare core is an i...

Embodiment 2

[0023] Such as figure 1 and figure 2 As shown in the communication system of the interconnected bare core and DSP / FPGA, the interconnected bare core is provided with a plurality of data interfaces, and a plurality of the data interfaces are used to connect with the DSP / FPGA, and each of the data interfaces is provided with a different A protocol conversion circuit, the protocol conversion circuit is used to convert different external data into a unified data protocol format into the interconnected bare core and convert the internal data of the interconnected bare core into a corresponding data interface according to the purpose of the data data protocol format.

[0024] The data interface includes a master interface, a slave interface, and a peer interface.

[0025] The master device interface includes: an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, and the interrupt interface is used to receive an interrupt request from the interconnec...

Images