Operation acceleration method and circuit for SSD (Solid State Disk) main control chip with high flexibility and low bandwidth

Abstract

The invention discloses an operation acceleration method and circuit for SSD main control chip with high flexibility and low bandwidth. The circuit comprises an interconnection array, an operation array and a memory, the operation array comprises a command reading unit, a write-back control unit and a plurality of operation modules; each operation module comprises an input queue processing unit, a logic operation unit and an output queue processing unit; according to the scheme, all the logic operation units are connected through the interconnection array, each operation module automatically sends the operation result to the next operation module through the interconnection array after completing the corresponding logic operation of the operation module, and the final operation result is stored in the memory through the writing control unit after all the operations are completed; and backward reading is carried out through the command reading unit. When different logical operations need to be carried out, only the command data packets of the corresponding levels need to be edited and input into the acceleration circuit, so that the efficiency and the flexibility of the logical operations are greatly improved.

Description

technical field [0001] The invention relates to the field of chip circuit design, in particular to an operation acceleration method and circuit of a high-flexibility and low-bandwidth SSD main control chip. Background technique [0002] SSD data storage has gradually become the main storage medium for consumer device data storage and cloud storage. For SSD data storage, data error correction is of great significance, especially for personal key data and data related to government agencies. The SSD main control chip is the brain of the SSD storage device, and its error correction performance and encryption and decryption performance directly determine the durability of the SSD hard disk. [0003] At present, the error correction function and encryption and decryption functions of the SSD main control chip are all realized by a fixed acceleration circuit that implements a specific error correction algorithm or encryption and decryption algorithm. This circuit can only achieve...

AI Technical Summary

Problems solved by technology

[0004] To this end, it is necessary to provide a technical solution for the operation acceleration circuit of the SSD main control chip with high flexibility and low bandwidth, so as to solve the problems of fixed computing power and poor flexibility of the SSD main control chip in the prior art.

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