Substrate and preparation method thereof, chip packaging structure and packaging method thereof

Abstract

The invention relates to a substrate and a preparation method thereof, a chip packaging structure and a packaging method thereof. The substrate includes: a substrate body; a first pad formed on the surface of the substrate body; a second pad formed on the surface of the substrate body; a dielectric layer, Formed on the surface of the substrate body, the dielectric layer has a first window and a second window, the first window exposes the first pad, the second window exposes the second pad, and the first window has In the first empty space, there is a second empty space in the second window, and the volume of the first empty space is greater than the volume of the second empty space. The volume of the first empty space of the substrate is greater than the volume of the second empty space, providing a larger space for the first solder than the second solder, so as to buffer the height difference between the first protrusion and the second protrusion, In order to achieve coplanarity, in the welding stage, the first protrusion and the first welding pad, and the second protrusion and the second welding pad can all be fixed and connected well, thereby improving the welding performance.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a substrate and a preparation method thereof, a chip packaging structure and a packaging method thereof. Background technique [0002] Packaging is the process of assembling integrated circuits into chip final products. It is to put the integrated circuit die (Die) produced by Foundry on a substrate that acts as a load bearing, lead out the pins, and then fix and package them as a whole. Usually, the chip can be packaged by flip chip packaging technology. Flip chip packaging technology is one of the bare chip packaging technologies. Metal bumps are made on the electrode area of ​​the chip, and then the metal bumps are connected to the electrode area on the printed substrate. Pressure welding connection, the footprint of the package is basically the same as the chip size, and it is the smallest and thinnest of all packaging technologies. However, due to the different positi...

AI Technical Summary

Problems solved by technology

However, due to the different positions of the metal bumps, the height of the metal bumps relative to the chip is not uniform, which will result in that the lower bumps cannot be connected to the substrate during the bonding connection, which will reduce the chip yield.

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