Linear interval expansion method for rapid frequency locking and cycle slip elimination

A linear interval, frequency locking technology, applied in the field of wireless communication, can solve the problems of slow locking speed, metastability, small gain, etc., to achieve the effect of speeding up the locking process and eliminating the phenomenon of cycle slip
CN112953529AActive Publication Date: 2021-06-11SHANGHAI JIAO TONG UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI JIAO TONG UNIV
Publication Date
2021-06-11

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Abstract

The invention discloses a linear interval expansion method for rapid frequency locking and cycle slip elimination, which comprises the following steps: dividing a phase discrimination interval into a plurality of linear subintervals with the length of 2[pi], and when the phase deviation exceeds + / -[pi], carrying out linear expansion, enabling the phase frequency detector for linear expansion and the charge pump to output constant current representing + / -2[pi] and convert a phase discrimination interval into a phase opposite to the phase discrimination interval so as to ensure that the output current is correct and neglect phase error information of + / -2[pi] so as to thoroughly avoid generation of cycle slip. According to the invention, the cycle slip phenomenon can be fundamentally avoided. A linear phase discrimination interval is expanded to + / -16[pi], and meanwhile, the number of branches of a constant current source is increased for further expansion, so that the expansion of the linear interval does not cause a metastable state.
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Description

technical field

[0001] The invention relates to a technology in the field of wireless communication, in particular to a method for fast frequency locking and cycle-slip elimination linear interval extension. Background technique

[0002] In the field of wireless communication, phase-locked loops (PLL, Phase Locked Loops) provide accurate local oscillation signals for signal modulation and demodulation, and at the same time, fast frequency hopping is also required for PLL. A common PLL compares the input reference clock and the feedback clock to obtain the control signal UP / DN for controlling the charge pumping / discharging current, and converts it into a voltage signal driving a voltage-controlled oscillator through a loop filter to form a closed circuit. negative feedback loop. The traditional charge pump (CP) has a limited phase detection interval, and for a large phase deviation, a small gain will be generated, which will slow down the locking speed. At the same time, du...

Claims

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