Method for improving chip testing efficiency
A technology for chip testing and high efficiency, which is applied in the direction of faulty hardware testing methods, software testing/debugging, and detection of faulty computer hardware. The process is smooth, the test time is saved, and the test efficiency is high.
Pending Publication Date: 2021-06-29
无锡市软测认证有限公司
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Problems solved by technology
[0004] The present invention provides a method for improving the efficiency of chip testing, which can effectively solve the problem that the current chip testing method proposed in the above-mentioned background technology has a low testing frequency for the chip, cannot quickly test the chip, and the testing frequency of the chip is low. The test time is extended, and the test efficiency is low
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Embodiment
[0075] Example: such as Figure 1-39 As shown, the present invention provides a kind of technical scheme, a kind of method for improving chip test efficiency, comprises following test steps:
[0076] S1. Analyze the test specifications of the chip under test to understand the information about the items, pins and patterns that need to be tested; for the items, pins and patterns that need to be tested, the tester determines the number of board channels that need to be used according to the test specifications. Determine whether it is within the existing channel coverage, and select the appropriate channel accordingly, and classify the test items. In the case of excessive current or excessive voltage in the chip test item, choose to use the SMU channel for high-current and high-precision measurement;
[0077] Based on the upper and lower limits of the test program in V50, get the corresponding settings according to the test items and the number of test parameters under each test...
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The invention discloses a method for improving chip test efficiency, which comprises the following test steps: S1, analyzing test specifications of a tested chip, and knowing related information of items, pins and patterns needing to be tested, and S2, creating a project, and carrying out basic setup before the test, by knowing the related information of the tested chip and the items needing to be tested, the pins and the pin group are defined, so that the plurality of pins are edited in the pin group, which is convenient for direct taking, test item setting, test code writing, DLL generation, loading operation, and finally test and debugging of the test items in the later period, so that the purpose of testing is achieved, the test is carried out one by one during testing, compared with other test items, the test of a single test item can be ensured to be more accurate, the test is enabled to be more orderly, the test process is enabled to be smooth, the test time is saved, the test frequency is improved, and the test efficiency is enabled to be higher.
Description
technical field [0001] The invention relates to the technical field of chip testing, in particular to a method for improving chip testing efficiency. Background technique [0002] Chip testing is a relatively big problem, which directly runs through the entire chip design and mass production process. Testing is mainly the process of using manual or automatic means to run or measure a certain software system. The purpose is to check whether it meets the specified requirements. Need or clarify the difference between the expected result and the actual result, the performance of the chip can be grasped only after the chip is tested, so that the chip will not be used incorrectly; [0003] However, the current chip testing method has a low test frequency for the chip, and cannot quickly test the chip. The low test frequency of the chip prolongs the test time and the test efficiency is low. Contents of the invention [0004] The present invention provides a method for improving ...
Claims
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IPC IPC(8): G06F11/22G06F11/36G06F8/41
CPCG06F11/2205G06F11/2273G06F11/3684G06F8/41
Inventor 钱裕香袁宝弟张健
Owner 无锡市软测认证有限公司