Merging tree sorting device, sorting system and sorting method

Abstract

The invention provides a merging tree sorting device, sorting system and sorting method. The sorting device comprises at least two kinds of double-tone and half-sorting modules with different output data quantities and a cache module; the double-tone and half-sorting modules with different output data quantities are connected from the bottom layer to the top layer according to the sequence of the output data quantities from small to large to form a merging tree structure, and a cache module is connected between every two adjacent double-tone and half-sorting modules with different output data quantities; the cache module is used for caching and accumulating data output by the previous layer of double-tone and half-sorting module to meet the requirement of the number of input data of the next layer of double-tone and half-sorting module; and each double-tone and half-sorting module is used for performing double-tone sorting on the two ordered sequences, completing sorting and output of one of the ascending sequence and the descending sequence in the double-tone sorting process, and blocking sorting and output of the other sequence. According to the scheme, multiple data can be output in one clock period, and the sorting efficiency can be improved.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a merge tree sorting device, a sorting system and a sorting method. Background technique [0002] Sorting plays a key role in many application scenarios, such as data mining, pattern recognition, etc. With the explosive growth of data volume, it is becoming more and more important to reduce sorting delay and increase sorting throughput in the process of sorting large-scale data. Considering the characteristics of parallelism and reconfigurability of FPGA (Field Programmable Gate Array, Field Programmable Gate Array), it is a good choice to implement the sorting algorithm using FPGA. [0003] When deploying sorting algorithms on FPGA, in order to achieve sorting of any data scale, the merge sorting algorithm is usually chosen. However, the common merge algorithm can only output one data per clock cycle, which greatly limits the throughput of the sorting algorithm and inc...

AI Technical Summary

Problems solved by technology

However, the common merge algorithm can only output one data per clock cycle, which greatly limits the throughput of the sorting algorithm and increases the delay.

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