[0046] In order to make the objects, technical solutions, and advantages of the present application, the present application will be further described in detail below with reference to the accompanying drawings.
[0047] Please refer to Figure 8 It shows the structure flow chart of the gallium nitride power device gate driving circuit provided by one embodiment of the present application. The gallium nitride power device gate driving circuit may include a narrow pulse generating circuit 810, a high voltage level shift circuit 820, a dynamic unsmapled state generation circuit 830, a common mode shield logic 840, an RS flip-flop 850, and a buffer level 860.
[0048] Such as Figure 8 As shown, the input end of the narrow pulse generating circuit 810 is connected to the input terminal IN_H of the gallium nitride power device gate driving circuit, and the first output terminal of the narrow pulse generating circuit 810 is connected to the first input of the high voltage level shift circuit 820. The second output terminal RESET of the narrow pulse generating circuit 810 is connected to the second input of the high voltage level shifting circuit 820, and the power supply end of the narrow pulse generating circuit 810 is connected to the low voltage side power source Vcc, and the narrow pulse generating circuit 810 logically The end is connected to the chip; the first output terminal A of the high voltage level shift circuit 820 3 The second output end B of the high voltage level shifting circuit 820 is connected to the first output of the dynamic unsmarks, and the first input of the common mode shield logic 840, the second output terminal of the high voltage level shift circuit 820. 3 The second output terminal of the dynamic non-symmetrical state generating circuit 830 and the common mode shield logic 840, respectively; the first output terminal of the common mode shield logic 840 and the reset input terminal of the RS flip-flop 850 E2 Connected, the second output terminal of the common mode shield logic 840 and the set input terminal of the RS trigger 850 E2 Connected; the same phase output terminal Q of the RS flip-flop 850 is connected to the first input of the buffer stage 860 and the first input of the dynamic non-symmetrical state generation circuit; the inverting output terminal Qb and dynamic non-symmetrical state generation circuits of the RS flip-flop 850 The second input is connected; the buffer level output is used as the output terminal HO of the gallium nitride power device gate driving circuit; the common mode shield logic 840, the power supply terminals of the RS flip-flop 850, and the buffer level 860 are connected to the high voltage side power supply Vb, respectively. The common mode shielding logic 840, the RS flip-flop 850, and the buffer level 860 are connected to the high pressure zone floating, respectively; the high voltage level shift circuit 820 also includes a latch, dynamic non-symmetrical state generation circuit 830 for Dynamically changing the balance point at the time of the power supply voltage transient, the latch is shifted upward when the balance point changes, to control the output signal of the gallium nitride power device gate driving circuit unchanged.
[0049] The circuit structure of the high voltage level shift circuit 820, the dynamic unsmapped logic 840, and the RS flip-flop 850 is described below.
[0050] 1) High voltage level shift circuit 820;
[0051] High voltage level shift circuit 820 can include: first switch N LD10 , Second switch N LD11 , First diode D 11 , Second diode D 12 And latch, latch includes first PMOS tube P 1 And second PMOS pipe P 2. Among them, the first switch N LD10 The gate is connected as the first input of the high voltage level shifting circuit 820, and the second switch N is connected. LD11 The gate is connected to the RESET as the second input of the high voltage level shifting circuit 820; the first switch N LD10 And the second switch N LD11 Source and substrates GND; first switch N LD10 Oclectic, second diode D 12 Negative electrode, first PMOS pipe P 1 Oil and second PMOS Pipe P 2 After the gate interconnection, the first output terminal A as the high voltage level shift circuit 820 is used. 3 Second switch N LD11 Different, first diode D 11 Negative electrode, second PMOS pipe P 2 Leakage and first PMOS tube P 1 After the gate interconnection, the second output terminal B as the high voltage level shift circuit 820 3 First PMOS Pipe P 1 And second PMOS pipe P 2 The source is connected to the high pressure side power source Vb, respectively; the first diode D 11 And the second diode D 12 The positive electrode is connected to the high pressure zone floating VS, respectively.
[0052] The first point in which the first switch and the second switch may be an NLDMOS device, or an LDMOS device, and may be other power devices such as IGBT, JFET, and the like.
[0053] The second point in which the first diode and the second diode may be a diode, or a base-emitter diode or a MOS tube of a triode, which is a clamping A. 3 And B 3 The voltage of the point can also be used in parallel with the first PMOS tube P. 1 And second PMOS pipe P 2 The source leaks are implemented.
[0054] The third point in which it needs to be explained is that the first PMOS pipe P 1 And second PMOS pipe P 2 The length ratio can be consistent or inconsistent.
[0055] 2) Dynamic asymmetric state generation circuit 830;
[0056] Dynamic non-symmetrical state generation circuit 830 can include: first NMOS tube N 3 And the second NMOS tube N 4. Among them, the first NMOS pipe N 3 Source and second NMOS pipe N 4 The source is connected to the high voltage zone floating in the high pressure zone; the first NMOS tube N 3 The drain is a first output terminal and a of the dynamic non-symmetric state generation circuit 830. 3 Connected; second NMOS tube N 4 The drain is a second output terminal and B as dynamic inhitty state generating circuit 830. 3 Connected; the first NMOS pipe N 3 The gate is connected as the first input of the dynamic non-symmetric state generation circuit 830 and the Q, the second NMOS tube N 4 The gate is connected to the Qb as the second input terminal of the dynamic non-symmetrical state generating circuit 830.
[0057] It should be noted that the latch can be made by the latch tube, or other latch to be used to a negative gate-source voltage or a negative base-emitter voltage opening device, as long as the first NMOS tube N is guaranteed 3 And the second NMOS tube N 4 The current capacity is much lower than the first PMOS pipe P in the latch. 1 And second PMOS pipe P 2 Current capability.
[0058] 3) common mode shielding logic 840;
[0059] The common mode shield logic 840 can include: first inverter INV 7 , Second inverter INV 8 First and non-door NAND 9 Second and non-door NAND 10 And third with non-door NAND 11. Among them, the first inverter INV 7 The input terminal as the second input terminal of the common mode shielding logic 840 and B 3 Connected, second inverter INV 8 The input terminal as the first input terminal of the common mode shielding logic 840 and a 3 Connected; first inverter INV 7 The output of the output and the first and non-door NAND, respectively 9 First input and second and non-door NAND 10 The first input is connected; the second inverter INV 8 The output of the output and the first and non-door NAND, respectively 9 Second input and third with non-door NAND 10 The first input is connected; the first and non-door NAND 9 Output and second and non-door NAND, respectively 10 Second input and third with non-door NAND 11 The second input is connected; the second and non-door NAND 10 The output is the first output end and R of the common mode shield logic 840.E2 Connected, third with non-door NAND 11 The output is the second output end and S of the common mode mask logic 840. E2 Connected.
[0060] 4) RS trigger 850;
[0061] RS trigger 850 can include: fourth and non-door NAND 12 And fifth and non-door NAND 13. Among them, the fourth and non-door NAND 12 The first input is the reset input terminal of the RS trigger 850. E2 , Fifth and non-door NAND 13 The first input is set as the set input terminal of the RS flip-flop 850 E2 Fourth and non-door NAND 12 Second input and fifth and non-door NAND 13 After the output is interconnected as the same phase output end Q of the RS trigger 850; fifth and non-door NAND 13 Second input and fourth and non-door NAND 12 The output is interconnected as the inverted output terminal Qb of the RS trigger 850.
[0062] Below Figure 8 The workflow of the gallium nitride power device gate drive circuit shown is described. Please refer to Figure 9 The input signal IN_H is a wider pulse signal, in order to reduce the conduction loss and reliability requirements of the high pressure switching device, first transform the rising edge and falling edges of IN_H to SET and RESET, respectively, by narrow pulse generating circuit 810. Narrow pulse signal, using SET driver N LD10 Using Reset Drive N LD11. Suppose the initial state determines the initial state of the RS flip-flop, so that HO is low, p 2 And N 3 Turn off, p 1 And N 4 Open, A 3 The initial state is logic high, B 3 The initial state is logic low. In t 1 Time, SET signal is effective, N LD10 Open, make A 3 The potential becomes logic low, resulting in P 2 Open and P 1 Shut down, B 3 The potential becomes logic high, after the common mode shield circuit 840, s E2 The potential becomes logic low and r E2 The potential becomes a logic high level such that the in-phase output terminal Q of the RS trigger outputs 850 out of the high level signal, and the two output signals of the RS flip-flop 850 feed back to N. 3 And N 4 Gate, make N 3 Open and N 4 Turn off. In t 2 After the moment, the SET signal is no longer effective, under the control of the feedback signal, A 3 The potential continues to keep the logic low, and B 3 The potential continues to maintain a logic high level. In t 3 Time, RESET signal is valid, N LD11 Open, make B 3 The potential becomes logic low, resulting in P 1 Open and P 2 Shut down, A 3 The potential becomes logic high, after the common mode shield circuit 840, s E2 The potential becomes logic high and r E2 The potential becomes a logic low, so that the in-phase output terminal Q of the RS trigger 850 outputs a low level signal, and the two output signals of the RS flip-flop 850 feed back to N. 3 And N 4 Gate, make N 3 Turn off and n 4 Open. After T4, the RESET signal is no longer valid, under the control of the feedback signal, A 3 The potential continues to keep the logic high, and B 3 The potential continues to keep the logic low.
[0063] When the DV / DT transient noise signal is applied to VS and VB, a 3 And B 3 The voltage of the node is slightly behind the rising speed of VB, making P 1 P 2 At the same time, there is always a 3 And B 3 Provide a displacement current, the latch will make a 3 And B 3 The voltage rapidly lifts. When the DV / DT speed is too fast, the displacement current will still pass D. 11 And D 12 Make a 3 And B 3 The voltage is characterized by a logic low in the VS side, which is masked by common mode shielding logic 840. But at this time, the completely symmetrical latch is in its non-steady state, such as Figure 10 The solid round position indicated that VS and VB after transient, the latch cannot determine the state transition in which the output is high, and the state transition in the output is low, in N 3 And N 4 Under the action, P 1 P 2 The latch structure configured as a non-symmetrical state. At this time, it is called an asymmetric latch, i.e., when the output initial state is high, the non-symmetric latch state of the DV / DT time period is Figure 10 The pentagon position is shown, and when the DV / DT is over, the state of the latch will inevitably return to the output high level. Similarly, when the output initial state is low, the state of the asymmetric latch is like Figure 10 The triangular position is described. When the DV / DT is over, the state of the latch will inevitably return to the output low state. The asymmetric latch eliminates A from the source 3 And B 3 The problem of differential mode noise in the common mode noise caused by the parametric parameters of the node, there is no need for additional RC (Resistor-Capacitance, Resistivity) filtering circuit, which is great to reduce the channel transmission delay. The ability to improve the anti-transient noise interference of the chip is improved.
[0064] Figure 11 When the gallium nitride power device gate driving circuit output is low, the simulation waveform of the influence of DV / DT transient noise, from Figure 11 As can be seen in the initial state, the reset input end of the RS trigger 850 is a logic low and the setting input is logic high; during DV / DT transient noise, A 3 And B 3 The voltage is manifested as a logic low with respect to VS, and the zero signal is filtered after the common mode elimination logic 840, and the state of the latch will gradually recover. Due to the same zero time 1 P 2 At the same time, there will be a small joint process after the DV / DT transient noise, then B 3 Gradually reduce VS (logic low) and A 3 Gradually increase to VB (logic high). In this process, the input state of the RS trigger 850 is always unaffected, so the output hold logic is not changed.
[0065] Figure 12 When the gallium nitride power device gate driving circuit is output to be high, the simulation waveform of the influence of DV / DT transient noise, from Figure 12 As can be seen in the initial state, the reset input end of the RS trigger 850 is a logic high and the setting input is a logic low; during the DV / DT transient noise, A 3 And B 3 The voltage is manifested as a logic low with respect to VS, and the zero signal is filtered after the common mode elimination logic 840, and the state of the latch will gradually recover. Due to the same zero time 1 P 2 At the same time turned on, therefore, the DV / DT transient noise will have a small group of commonly rising processes, then A 3 Gradually reduced to VS (logic level) and B 3 Gradually increase to VB (logic high). In this process, the input state of the RS trigger 850 is always unaffected, so the output hold logic high is constant.
[0066] Please refer to Figure 13 It shows the structure flow chart of the gallium nitride power device gate driving circuit provided by one embodiment of the present application. The gallium nitride power device gate driving circuit can include: narrow pulse generating circuit 1310, high voltage level shifting circuit 1320, dynamic unsmapped state generation circuit 1330, preamplifier 1340, common mode shield logic 1350, RS trigger 1360 And buffering level 1370.
[0067] Such as Figure 13 As shown, the input end of the narrow pulse generating circuit 1310 serves as the input terminal IN_H of the gallium nitride power device gate driving circuit, and the first output terminal SET of the narrow pulse generating circuit 1310 is connected to the first input of the high voltage level shift circuit 1320. The second output terminal RESET of the narrow pulse generating circuit 1310 is connected to the second input of the high voltage level shifting circuit 1320, and the power supply end of the narrow pulse generating circuit 1310 is connected to the low pressure side power source Vcc, and the narrow pulse generating circuit 1310 logically The end is connected to the chip; the first output terminal of the high voltage level shift circuit 1320 4 The second output terminal B of the high voltage level shift circuit 1320 is connected to the first output terminal of the dynamic non-symmetrical state generating circuit 1330 and the first input of the preamplifier 1340. 4 The second input terminal of the dynamic non-symmetrical state generation circuit 1330 and the front amplifier 1340, respectively; the first output terminal E of the preamplifier 1340 is connected to the first input of the common mode shield logic 1350; The second output terminal T of the amplifier 1340 is connected to the second input of the common mode shield logic 1350; the first output terminal of the common mode shield logic 1350 and the reset input terminal of the RS flip-flop 1360 E3 Connectively, the second output terminal of the common mode shield logic 1350 and the set input terminal of the RS flip-flop 1360 E3 Connectively; the same phase output terminal Q of the RS flip-flop 1360 is connected to the first input of the buffer level 1370 and the first input of the dynamic unsmapled state generating circuit; the inverting output terminal Qb and the dynamic non-symmetrical state of the RS flip-flop 1360 generate circuits The second input is connected; the buffer level output is used as the output terminal HO of the gallium nitride power device gate driving circuit; the power supply terminals of the common mode shielding logic 1350, the RS flip-flop 1360, and the buffer level 1370 are connected to the high voltage side power supply Vb, respectively. The common mode shielding logic 1350, the RS flip-flop 1360 and the buffer level 1370 are logically connected to the high pressure zone floating Vs. The high voltage level shift circuit 1320 includes a latch, dynamically non-symmetric state generation circuit 1330 for dynamically changing the balance point at the time of the power supply voltage transient, and the latch is shifted when the balance point changes. Up to a steady state to control the output signal of the gallium nitride power device gate driving circuit unchanged.
[0068] The circuit configuration of the high voltage level shift circuit 1320, the dynamic unsmapped state generation circuit 1330, the preamplifier 1340, the common mode shielding logic 1350, and the RS flip-flop 1360 are introduced.
[0069] 1) High voltage level shift circuit 1320;
[0070] High voltage level shift circuit 1320 can include: first switch NLD12 , Second switch N LD13 , First diode D 13 , Second diode D 14 And latch, latch includes first PMOS tube P 3 And second PMOS pipe P 4. Among them, the first switch N LD12 The gate is connected to the SET as the first input of the high voltage level shifting circuit 1320, and the second switch N is connected. LD13 The gate is connected to the RESET as the second input of the high voltage level shift circuit 1320; the first switch N LD12 And the second switch N LD13 Source and substrates GND; first switch N LD12 Oclectic, second diode D 14 Negative electrode, first PMOS pipe P 3 Oil and second PMOS Pipe P 4 After the gate interconnection, as the first output terminal of the high voltage level shift circuit 1320 4 Second switch N LD13 Different, first diode D 13 Negative electrode, second PMOS pipe P 4 Leakage and first PMOS tube P 3 After the gate interconnection, the second output terminal B as the high voltage level shift circuit 1320 4 First PMOS Pipe P 3 And second PMOS pipe P 4 The source is connected to the high pressure side power source Vb, respectively; the first diode D 13 And the second diode D 14 The positive electrode is connected to the high pressure zone floating VS, respectively.
[0071] The first point in which the first switch and the second switch may be an NLDMOS device, or an LDMOS device, and may be other power devices such as IGBT, JFET, and the like.
[0072] The second point in which the first diode and the second diode may be a diode, or a base-emitter diode or a MOS tube of a triode, which is a clamping A. 4 And B 4 The voltage of the point can also be used in parallel with the first PMOS tube P. 3 And second PMOS pipe P 4 The source leaks are implemented.
[0073] The third point in which it needs to be explained is that the first PMOS pipe P 3 And second PMOS pipe P 4 The length ratio can be consistent or inconsistent.
[0074] 2) Dynamic asymmetric state generation circuit 1330;
[0075] Dynamic non-symmetrical state generation circuit 1330 can include: third NMOS tube N 5 , Fourth NMOS tube N 6 , Third resistance R 8 And the fourth resistance R 9. Among them, the third NMOS pipe N 5 Source and fourth NMOS pipe N 6 The source interconnects are connected to the high pressure zone floating vs; the third resistance R 8 The first end and the third NMOS tube n 5 Open, third resistance R 8 The second end as the first output terminal of the dynamic non-symmetrical state generation circuit 1330 and a 4 Connected; fourth resistance R 9 The first end and the fourth NMOS pipe N 6 Dialect, fourth resistance R 9 The second end as the second output terminal and B of the dynamic non-symmetric state generation circuit 1330 4 Connected; the third NMOS pipe N 5 The gate is connected as the first input of the dynamic non-symmetrical state generation circuit 1330; the fourth NMOS pipe N 6 The gate is connected as the second input terminal of the dynamic non-symmetrical state generating circuit 1330 to QB.
[0076] It should be noted that the latch is composed of the latch tube, or other latch other for the negative gate-source voltage or negative base-emitter voltage opening device, as long as the third NMOS tube N is guaranteed 5 And fourth NMOS tube N 6 The current capacity is much lower than the first PMOS pipe P in the latch. 3 And second PMOS pipe P 4 Current capability.
[0077] 3) Preamplifier 1340;
[0078] The preamplifier 1340 can include: a first p-type switch P 5 , Second p-type switch P 6 , First resistance R 10 And second resistance R 11. Among them, the first P-type switch P 5 The gate is used as the first input terminal of the preamplifier 1340, the second p-type switch P 6 The gate is the second input of the preamplifier 1340; the first P-type switch P 5 Leakage, first resistance R 10 The first end is connected to each other as the first output E of the preamplifier 1340; the second p-type switch P 6 Leakage, second resistance R 11 The first end is connected to the second output terminal T of the preamplifier 1340; the first resistance R 10 Second end and second resistance R 11 The second end is connected to the high pressure zone floating vs, and the first P-type switch P 5 Source and second p-type switch P 6 The source interconnect is connected to the high pressure side power source Vb.
[0079] 4) common mode shielding logic 1350;
[0080] The common mode mask logic 1350 can include: sixth and non-door NAND 14 , Seventh and non-door NAND 15 And eighth and non-door NAND 16. Among them, the sixth and non-door NAND 14 First input and seventh and non-door NAND 15 After the first input is interconnected, the second input of the common mode mask logic is connected to T, the sixth and non-door NAND 14 Second input and eighth and non-door NAND 16 After the first input is interconnected, the first input of common mode mask logic is connected to E; the sixth and non-door NAND 14 The output of the output and the seventh and non-door NAND, respectively 15 Second input and eighth and non-door NAND 16 The second input is connected; the seventh and non-door NAND 15 The output of the output is the first output end and R of common mode mask logic. E3 Connected, eighth and non-door NAND 16 The output of the output is the second output of common mode mask logic and S E3 Connected.
[0081] 5) RS trigger 1360;
[0082] RS trigger 1360 can include: fourth and non-door NAND 17 And fifth and non-door NAND 18. Among them, the fourth and non-door NAND 17 The first input is the reset input terminal RS trigger 1360. E3 , Fifth and non-door NAND 18 The first input is set as the set input terminal of the RS flip-flop 1360 E3 Fourth and non-door NAND 17 Second input and fifth and non-door NAND 18 The output is interconnected as the same phase output end Q of the RS trigger 1360; fifth and non-door NAND 18 Second input and fourth and non-door NAND 17 The output end is connected to the inverted output terminal Qb of the RS trigger 1360.
[0083] In this embodiment, the logic effect of the preamplifier 1340 is consistent with the inverter in the common mode shield logic 1350, and its response threshold is much lower than the inverter, broaden the response range of the signal, and can improve the VS of the chip. Negative biasing capacity.
[0084] Figure 13 The workflow of the gallium nitride power device gate driving circuit shown in the medium Figure 8 The workflow of the gallium nitride power device gate driving circuit shown is the same, and details are not described again.
[0085] One of ordinary skill in the art will appreciate that all or some of the steps of implementing the above embodiment can be accomplished by hardware, or by a program to instruct the hardware completed, the program can be stored in a computer readable storage medium, the above The storage medium mentioned can be read-only memory, disk, or disc.
[0086] The above is not intended to limit the embodiments of the present application, and any modifications, equivalents, improvements, etc. according to the spirit and principles of the present application, should be included within the scope of the present application embodiment.
