DDR4 address control line mapping and Ball arrangement method for T-type topological structure

Abstract

The invention provides a DDR4 (Double Data Rate 4) address control line mapping and Ball arrangement method for a T-shaped topological structure, which meets the requirements of signal quality and time sequence margin. The mapping and arranging method is characterized in that according to the arrangement of the positions of the via holes, adjacent addresses / control lines of the via holes are distributed in one group during mapping; in other words, when the DDR controller is configured, one delay configuration is shared. Point-to-point signals are distributed in one group corresponding to the same memory. According to the arrangement of the pins of the DDR controller, the arrangement positions of the pins in the same group are adjacent so as to ensure that time delays are close. And the address / control signals in the same group are wired in the same inner layer. The quality of the comprehensive eye pattern is optimal, and the difficulty of equilong winding of the PCB can be reduced while the time sequence margin is maximized. While special PCB equal-length processing is not needed, the maximization of the address / control line time sequence margin is met, the PCB design is simplified, the wiring area is reduced, and the consistency of hardware design is ensured.

Description

technical field [0001] The invention relates to the field of system-on-chip (SOC) package arrangement and address mapping, in particular to a DDR4 address control line mapping and Ball arrangement method for a T-shaped topology. Background technique [0002] With the improvement of the main frequency of the system, the application of high-definition cameras, and more and more algorithm applications, such as face recognition, mobile phones, and smart camera systems, the data rate becomes higher and higher. The speed of DDR memory used in the system has also increased, and the number of memories has also increased. What follows is the signal integrity problem caused by the rate increase, and the topology of multiple memories also makes the signal extremely deteriorated. The two address / control topologies commonly used in the industry have their own advantages and disadvantages: [0003] T-type topology, commonly used in two-chip memory solutions, not suitable for multiple chi...

AI Technical Summary

Problems solved by technology

Its disadvantage is that in high-speed application scenarios, the delay difference from the bifurcation point of the T-shaped structure to the two memories affects the quality of the eye diagram and the margin of the setup and hold time at the same time.

In order to ensure that the design meets the required signal quality and timing margin, it is necessary to control the delay of branches, etc., and at the same time control the delay difference of multiple signal lines in the group. Strict requirements for PCB design will lead to increased wiring area.

At the same time, it is easy to be overlooked that due to the difference in the wiring delay per unit length between the outer layer and the inner layer of the PCB, it will lead to wiring that looks equal in length. In fact, the delay is not consistent, and the signal quality control requirements are delivered to the customer. There are uncontrollable factors

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