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Method for forming product structure having porous regions and lateral encapsulation

A technology of hole area and metal area, applied in the field of electronic products, can solve the problem of not allowing independent voltage domain decoupling

Pending Publication Date: 2021-08-17
MURATA MFG CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This solution does not allow decoupling of separate voltage domains

Method used

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  • Method for forming product structure having porous regions and lateral encapsulation
  • Method for forming product structure having porous regions and lateral encapsulation
  • Method for forming product structure having porous regions and lateral encapsulation

Examples

Experimental program
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Embodiment Construction

[0078] Hereinafter, steps for manufacturing a structure in which a capacitor is formed according to an embodiment will be described.

[0079] This embodiment addresses existing deficiencies of the prior art related to the complexity of forming two capacitors that are not electrically coupled together in the porous region.

[0080] figure 2 is a side view of a structure including a semiconductor substrate 200 . The semiconductor substrate may include silicon portions on which electrical components such as transistors, diodes and resistors have been formed. Above these components an interconnection network has been formed and comprises a plurality of metallization layers connected together using vias in a manner known per se. The top of the semiconductor substrate may include pads (electrical connection pads) for making contact with components placed above the substrate and a top metallization layer of the substrate. As an example, the pads may be metal regions comprising al...

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Abstract

Method for forming product structure having porous regions and lateral encapsulation A method for fabricating a structure, the structure comprising: - an insulating layer (201), - a first metal layer (203) above a first portion of the insulating layer, - a first porous region of anodic oxide, above and in contact with the first metal layer, and - a second porous region of anodic oxide, surrounding the first porous region, in contact with a second portion of the insulating layer adjacent to the first portion of the insulating layer, and in contact with the first metal layer, the second porous region forming an insulating region.

Description

technical field [0001] The present invention relates to the field of integration, and in particular to electronic products, related semiconductor products and methods of manufacturing the same. [0002] The invention relates more precisely to electronic components comprising porous regions. Background technique [0003] Today, silicon passive integration technology is available for industrial design. For example, the PICS technology developed by Murata Integrated Passive Solutions (Murata Integrated Passive Solutions) allows the integration of high-density capacitive components into silicon substrates. According to this technology, dozens or even hundreds of passive components can be efficiently integrated into a silicon chip. [0004] For example, in P. Banerjee et al. entitled "Nanotubular metal-insulator-metal capacitor arrays for energy storage (nanotube metal-insulator-metal capacitor arrays for energy storage)" (May 2009 in Natural technology ), describe metal-insul...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/522C25D11/04H01G4/10H01L49/02C25D11/02H10N97/00
CPCH01G4/10H01L23/5223H01L28/40H01L28/60C25D11/045C25D11/022H01G4/33H01L23/642H01L28/75H01L28/91
Inventor 弗雷德里克·瓦龙布里吉特·苏利耶久伊·帕拉特
Owner MURATA MFG CO LTD