Starting circuit for delay-locked loop (DLL)

Abstract

The invention relates to the technical field of microelectronics, aims to solve the problem of harmonic locking of a DLL, and provides a starting circuit structure suitable for an analog DLL. Harmonic locking of the DLL can be prevented by adding the starting circuit provided by the invention into the DLL, and the DLL can quickly enter a correct locking state. Therefore, according to the technical scheme used by the invention, the starting circuit for the DLL comprises a DLL main circuit and a DLL starting circuit, wherein the DLL main circuit comprises a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF) and a voltage controlled delay chain (VCDL); the VCDL is formed by cascading a plurality of delay units with adjustable delay; the delay control ends of all the delay units are connected with the output end Vctrl of the low-pass filter; and the input of the VCDL is a reference clock signal clk_ref. The method is mainly applied to analog DLL design and manufacturing occasions.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a delay phase-locked loop circuit and a starting circuit thereof. Background technique [0002] The development of synchronous VLSI (Very Large Scale Integration, VLSI) puts forward higher requirements on the clock calibration between modules in the system. As the frequency of the clock signal increases, the total phase error of the clock increases if the jitter and skew of the clock signal remain constant. The increased phase error will seriously affect the operation of the synchronous system, including the setup and hold time, the read time of data, and the accuracy of internal control signals. In order to reduce the clock skew, a simple fixed delay circuit can be used, but the delay time of this circuit is different for different process, voltage and temperature (Process, Voltage, Temperature, PVT) conditions, and the system Variations in clock frequency can also ca...

AI Technical Summary

Problems solved by technology

When the DLL is harmonically locked, the delay of VCDL is no longer one cycle of the reference clock signal, which will cause the various modules in the system to not work normally, thus causing the system to fail, so measures should be taken to prevent DLL from being harmonically locked.

In the prior art, one method is to use an exponential digital-to-analog converter (Digital-to-Analog Converters, DAC) and a low-dropout linear regulator (Low Dropout Regulator, LDO) to design the start-up circuit of the DLL. The advantage is that the range of preventing harmonic locking is large, but the starting circuit uses modules such as DAC and LDO, and the design is more complicated

Another method is to use D flip-flops, NAND gates and NOT gates to design a DLL start-up circuit with a simple structure, but it takes a long time for the DLL to lock correctly from start-up

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