Startup circuit for delay locked loop

Abstract

The invention relates to the technical field of microelectronics, aiming at the problem of harmonic locking of DLL, the invention aims to propose a startup circuit structure suitable for simulating DLL, adding the startup circuit proposed by the invention to the DLL can prevent harmonic locking of DLL, Enables the DLL to quickly enter the correct locked state. To this end, the technical solution adopted by the present invention is that the startup circuit for delay-locked loop includes a DLL main circuit and a DLL startup circuit; the DLL main circuit includes a frequency discriminator PFD, a charge pump CP (Charge Pump), a low Pass filter LPF (Low Pass Filter) and voltage-controlled delay chain VCDL; VCDL is composed of multiple delay units with adjustable delay cascaded, the delay control terminal of all delay units and the low-pass filter The output terminal is connected to Vctrl and the input of VCDL. The invention is mainly applied to the design and manufacture occasions of simulating DLL.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a delay phase locked loop circuit and a start-up circuit thereof. Background technique [0002] The development of synchronous VLSI (Very Large Scale Integration, VLSI) puts forward higher requirements for clock calibration between modules in the system. As the frequency of the clock signal increases, the total phase error of the clock increases if the jitter and skew of the clock signal remain constant. The added phase error can seriously affect the operation of the synchronization system, including setup and hold time, data read time, and the accuracy of internal control signals. In order to reduce the offset of the clock, a simple fixed delay circuit can be used, but the delay time of this circuit is different for different process, voltage and temperature (Process, Voltage, Temperature, PVT) conditions, and the system Changes in clock frequency also cause delays to...

AI Technical Summary

Problems solved by technology

When the DLL is harmonically locked, the delay of VCDL is no longer one cycle of the reference clock signal, which will cause the various modules in the system to not work normally, thus causing the system to fail, so measures should be taken to prevent DLL from being harmonically locked.

In the prior art, one method is to use an exponential digital-to-analog converter (Digital-to-Analog Converters, DAC) and a low-dropout linear regulator (Low Dropout Regulator, LDO) to design the start-up circuit of the DLL. The advantage is that the range of preventing harmonic locking is large, but the starting circuit uses modules such as DAC and LDO, and the design is more complicated

Another method is to use D flip-flops, NAND gates and NOT gates to design a DLL start-up circuit with a simple structure, but it takes a long time for the DLL to lock correctly from start-up

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