Power semiconductor device packaging structure and manufacturing method thereof

Abstract

The invention relates to a power semiconductor device packaging structure and a manufacturing method thereof. The structure comprises a chip main body and a heat dissipation slide glass. The processing surface of the chip main body is provided with a source electrode pad and a grid electrode pad, and the back surface of the chip main body is provided with a drain electrode layer; the heat dissipation slide is attached to the back face of the chip body and electrically coupled with the drain electrode layer, the heat dissipation slide is provided with side supporting feet extending integrally, the back face is bent to the joint plane where the source electrode pad and the grid electrode pad are located through the side face of the chip body, and the drain electrode pad is formed at one end, at the joint plane, of the side supporting feet; a gap is kept between the side supporting foot and the side face of the chip body, so that the drain electrode pad can move relative to the source electrode pad and the grid electrode pad. According to the packaging structure provided by the invention, the chip manufacturing difficulty of the power semiconductor device is reduced, the production process flow is reduced, and the effect of improving the transistor effective region of the chip is achieved.

Description

technical field [0001] The present invention relates to the technical field of packaging of power semiconductor devices, in particular to a packaging structure of a power semiconductor device and a manufacturing method thereof. Background technique [0002] Existing power semiconductor devices generally use a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure, and the three poles of the source pad, drain pad and gate pad of the metal part are arranged on the processing surface of the chip. It can be electrically connected to the circuit board in use. In the structure of the MOSFET chip in the early stage of semiconductor manufacturing, the source pad and gate pad are on the front side of the wafer processing, and the drain layer is on the back side of the wafer. To the same side as the source pad, it is necessary to dig a slot on the chip to connect the drain layer on the back with the drain pad contact on the front. The deep groove and the corresponding is...

AI Technical Summary

Problems solved by technology

The technical prejudice under the relevant patents is that the gate contact pad, source contact pad and drain contact pad are all arranged on the front side, and the drain contact pad is located on the front side. The necessary deep trench excavation and corresponding isolation will increase the difficulty of chip manufacturing and production process flow, and occupy the effective area of ​​the on-chip transistor

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