Test structure and test method

Abstract

The invention provides a test structure and a test method. The test structure comprises a first interconnection line layer and a contact layer, wherein the first interconnection line layer comprises at least one first test line; and the contact layer is located on the first interconnection line layer, the contact layer comprises a first contact structure and a plurality of second contact structures located on one side of the first contact structure, and the plurality of second contact structures and the first contact structure are located on the same first test line and electrically connected with the same first test line. According to the test method, the resistance temperature coefficient of a resistor between a first contact structure and each second contact structure in a test structure is obtained, and then whether microdefects (such as grain defects and stress mismatch) exist in a first interconnection line layer or not is obtained according to the resistance temperature coefficient, so that the quality change of the interconnection line layer can be effectively monitored, initial screening can be provided for subsequent reliability test items such as electromigration and stress migration, and test resources are saved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a test structure and a test method. Background technique [0002] Test items such as electromigration and stress migration are important characterization methods for detecting the reliability of metal interconnection lines. However, when the reliability performance of the metal interconnection is not up to standard, it is usually necessary to detect the cause of failure of the metal interconnection structure by means of failure analysis and other technical means. However, the failure analysis period of the metal interconnection structure is long, and the cause of failure cannot be fed back in time. In addition, terminal defects, stress mismatch, and grain defects in the interconnect layer of the metal interconnect structure are not easy to be monitored in the actual wafer acceptability test, which easily leads to substandard wafers entering In subsequent tes...

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a test structure and test method to solve the problem that the defects in the interconnection layer are not easy to be detected

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