Method for optimizing differential via hole impedance, circuit board, equipment and storage medium

A differential via impedance, printed circuit board technology, applied in the direction of printed circuit, printed circuit manufacturing, electrical components, etc., can solve the problems of complex board manufacturing process, failure to meet design requirements, increase cost, etc., to improve link Impedance continuity, optimized via impedance, and the effect of reducing signal reflection

Pending Publication Date: 2021-11-02
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this design method can change the impedance at the via hole and reduce the impedance discontinuity, due to the different length of the via hole and the length of the stump, the size of the anti-pad is also different, which makes t

Method used

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  • Method for optimizing differential via hole impedance, circuit board, equipment and storage medium
  • Method for optimizing differential via hole impedance, circuit board, equipment and storage medium
  • Method for optimizing differential via hole impedance, circuit board, equipment and storage medium

Examples

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Effect test

Embodiment 1

[0034] In order to further illustrate the design method of the present invention, a specific via is taken as an example to describe in detail, as figure 1 The via design of a PCIe Gen4 link is given, in which the radius of the signal hole is 4mil, and the radius of the via pad (via pad) is 10mil. The signal traces on the via hole are changed from layer L1 to layer L5. Such as figure 2 A three-dimensional diagram of the via design of a PCIe Gen4 link in China is given. The target controlled impedance of the vias is 85ohm±2ohm.

[0035] Due to the high signal rate, the via hole has a 51mil via stub (via stub), so the signal hole is back-drilled, and the back-drilling depth is 41mil, such as image 3 The back-drilling of the vias is given, and only the back-drilling is performed for the signal holes. Such as Figure 4 It is a schematic diagram of a PCIe Gen4 via anti-pad design in Embodiment 1 of the present invention. Figure 4 The picture above is the anti-pad design of ...

Embodiment 2

[0062] Based on a method for optimizing differential via impedance proposed in Embodiment 1 of the present invention, Embodiment 2 of the present invention also proposes a printed circuit board, which is processed by a method for optimizing differential via impedance; Both the signal hole and the ground hole of the circuit board are back-drilled; and the depth of the back-drilled ground hole is not greater than the depth of the back-drilled signal hole.

[0063] Before performing the back drilling, calculate the thickness of the via stub according to the signal trace and the thickness of the printed circuit board; determine the depth of the signal hole back drilling according to the thickness of the via stub; according to the depth of the signal hole back drilling Depth determines the depth of the backdrilling of the ground hole;

[0064] The method of calculating the thickness of the via stub according to the signal trace and the thickness of the printed circuit board is: the...

Embodiment 3

[0072] Based on a method for optimizing differential via impedance proposed in Embodiment 1 of the present invention, Embodiment 3 of the present invention also proposes a differential via impedance optimization device for printed circuit boards, including:

[0073] memory for storing computer programs;

[0074] The processor is configured to implement the steps of a method for optimizing differential via impedance when executing the computer program.

[0075] Both the signal hole and the ground hole of the printed circuit board are back-drilled; and the depth of the back-drilled ground hole is not greater than the depth of the back-drilled signal hole.

[0076] Before performing the back drilling, calculate the thickness of the via stub according to the traces of the signal and the thickness of the printed circuit board; determine the depth of the signal hole back drilling according to the thickness of the via stub; according to the depth of the signal hole back drilling Dep...

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Abstract

The invention provides a method for optimizing differential via hole impedance, a circuit board, equipment and a storage medium. The method comprises the following steps of: calculating the thickness of a via hole stub according to the wiring of a signal and the thickness of a printed circuit board; determining the back drilling depth of a signal hole according to the thickness of the via hole stub; and determining the back drilling depth of a ground hole according to the back drilling depth of the signal hole, and performing back drilling on the signal hole and the ground hole of the printed circuit board to be subjected to differential via hole impedance optimization, wherein the back drilling depth of the ground hole is not greater than the back drilling depth of the signal hole. The invention further provides a circuit board, equipment and a storage medium based on the method. The impedance property of the via hole needs to be concerned when the high-speed link is designed, and for the ultra-high-speed signal hole with back drilling, the reference ground hole can be subjected to back drilling design besides optimizing the size of the anti-bonding pad, so that the via hole impedance can be further optimized, the link impedance continuity can be improved, the signal reflection can be reduced, and the signal transmission quality can be effectively improved.

Description

technical field [0001] The invention belongs to the technical field of printed circuit board design, and in particular relates to a method for optimizing differential via impedance, a circuit board, equipment and a storage medium. Background technique [0002] With the rapid development of microelectronics technology, the rising edge of the signal is getting faster and faster, and the transmission line effect produced by high-speed circuits is becoming more and more serious. For the current mainstream high-speed circuits, PCB engineers must adopt high-speed PCB design technology based on transmission line theory to ensure the normal operation of the circuit. The design and control of characteristic impedance is the core and foundation to solve the transmission line effect of high-speed circuits, and it has been paid more and more attention by PCB engineers and manufacturers. In order to obtain the final high-precision characteristic impedance circuit board products, it is n...

Claims

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Application Information

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IPC IPC(8): H05K3/00
CPCH05K3/00H05K3/0047H05K2203/0207
Inventor 荣世立
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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